Abstract: A microphone system implements multiple microphones on a single base. To that end, the microphone system has a base, and a plurality of substantially independently movable diaphragms secured to the base. Each of the plurality of diaphragms forms a variable capacitance with the base and thus, each diaphragm effectively forms a generally independent, separate microphone with the base.

Abstract: Methods and apparatus for correcting for circuit self-heating replicate a thermal characteristic of a component that may be coupled to a bias circuit. A bias circuit may include replication component coupled to a reference cell. The replication component may be included in a feedback loop with the reference cell to improve accuracy.

Abstract: Comparator systems are provided that include cross-coupled transistors which respond to a differential network that receives an input signal. The systems further include a control transistor connected across the cross-coupled transistors and a bias network configured to apply a bias voltage to the control transistor that is substantially the voltage across two transistors which are each biased into saturation. It has been found that this bias during the systems' acquire phase substantially stabilizes the systems' gain over variations in their total environment and that this stabilization enhances the systems' performance.

Abstract: An optical cross-connect switch comprises a base (216), a flap (211) and one or more electrically conductive landing pads (222) connected to the flap (211). The flap (211) has a bottom portion that is movably coupled to the base (216) such that the flap (211) is movable with respect to a plane of the base (216) from a first orientation to a second orientation. The one or more landing pads (222) are electrically isolated from the flap (211) and electrically coupled to be equipotential with a landing surface.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A multi-path digital power supply controller includes a first ADC (ADC1) coupled to the supply's output voltage Vout and arranged to provide an output which varies with Vout's low frequency components, and a second ADC (ADC2) coupled to Vout and arranged to provide an output which varies with Vout's high frequency components. A digital reference value is subtracted from the output of ADC1 to produce a low frequency digital error signal, and a summing circuit sums the low frequency digital error signal and the output of ADC2. Processing circuitry is arranged to produce an output which varies with the summed signal and is suitable for coupling to a power stage for use in regulating Vout. Preferably, ADC1 is a low-bandwidth high-resolution ADC and ADC2 is a high-bandwidth low-resolution ADC, both of which are low-cost components.

Abstract: Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.

Abstract: A frequency synthesizer includes a circuit which selectively outputs multiple output signals having different respective periods to drive the average period of a combined output signal to substantially equal a desired period.

Abstract: A method for placing a device in a selected mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first user-controlled time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input. The selected operating mode may be a reduced power consumption mode, for example, or another operating mode of the device, such as a daisy-chain mode of operation, or a mode that accommodates programming of analog input range.

Abstract: A compact Galois field parallel multiplier engine includes a multiplier circuit for multiplying together two polynomials with coefficients over a Galois field to obtain their product; a Galois field linear transformer circuit has a multiply input from the multiplier circuit for predicting the modulo remainder of the polynomial product for an irreducible polynomial; first and second polynomial inputs; the Galois field linear transformer circuit may include a plurality of cells configured in a matrix section and a unity matrix section wherein the unity matrix section cells represent the prediction of the remainder when the output of the multiplier circuit is a polynomial with a power less than the power of the irreducible polynomial.

Abstract: A synchronization pulse detector includes an absolute value independent shape detector for processing samples of an input signal having a synchronization pulse and a plurality of non-synchronization pulses to determine whether such samples have a predetermined sequence. The predetermined sequence includes a first and second absolute value independent time-varying portions and a first and second absolute value independent non-time varying portions. One of the first and second absolute value independent time-varying portions having a positive slope and the other one of the first and second absolute value independent time-varying portions having a negative slope.

Abstract: Improved capacitive sensor operation is achieved with improved discrimination between environmental drift and apparent drift attributable to human proximity to the sensor. A proximity algorithm detects conditions interpreted as indicating a user is close to, but not touching, a sensor. When such proximity is detected, ambient value calibration is halted, thereby avoiding treating the human's proximity as environmental drift requiring compensation and preventing miscalculation of calibration. The proximity algorithm employs two moving-average filters (implemented in hardware or software) to monitor the CDC output values over time and to make appropriate adjustments to a signal representing the ambient, while distinguishing environmental drift from proximity-induced pseudo-drift.

Abstract: A high speed program tracer providing compression using linear increment run length values, displacement values corresponding to discontinuities, and loop compression. A program count sequencer receives program count values from a processor, and outputs various program count values and signals to allow compression calculations to be made based upon linear increment run lengths, discontinuity detection, and detection of repeating instruction loops. Compression may be achieved using selected numbers of words to represent various compression values.

Abstract: A digital-to-analogue converter (DAC) (1) comprises a digital processing circuit (2) having an input register (10) to which data samples of a digital input signal are written at a data sampling rate (fs). A delay register (14) holds each data sample for one clock cycle of the data sampling rate (fs), and a subtracting circuit (15) sequentially produces difference values between consecutive ones of the data samples by subtracting the data sample in the delay register (14) from the input register (12) on each clock cycle of the data sampling rate (fs).

Abstract: A voltage circuit including a first amplifier having first and second inputs and having an output driving a current mirror circuit is provided. Outputs from the current mirror circuit drive first and second transistors which are coupled to the first and second input of the amplifier respectively. The base of the first transistor is coupled to the second input of the amplifier and the collector of the first transistor is coupled to the first input of the amplifier such that the amplifier keeps the base and collector of the first transistor at the same potential. The first and second transistors are adapted to operate at different current densities such that a difference in base emitter voltages between the first and second transistors may be generated across a resistive load coupled to the second transistor, the difference in base emitter voltages being a PTAT voltage.

Abstract: Transmission loss compensation is provided for receiver circuits in general, including an ATE receiver circuit having a voltage-to-current converter, such as a transconductance amplifier, that receives a distorted DUT signal and provides an output to a current-to-voltage converter, such as a transimpedance amplifier. The compensation circuit injects a compensation current into the current-to-voltage converter to compensate for transmission losses. The compensation circuit can be configured to inject a plurality of transient compensation currents with different respective time constants and peak values.

Abstract: Clock sources are provided which are especially useful for reducing phase noise in signal samplers that typically provide samples of an analog input signal in signal-conditioning systems such as analog-to-digital converters. This phase noise reduction is realized with the recognition that sampler noise is related to clock jitter by a ratio of the input signal's slew rate to the clock's slew rate. Clock embodiments include a frequency divider and a signal gate. The divider divides a first signal to provide a second signal with a slew rate lowered from the slew rate of the first signal and the gate passes the second signal when commanded by the first signal to thereby generate a clock signal.

Abstract: A N-bit segmented digital to analog converter (DAC) adapted to provide an analog signal output on the basis of a digital input code, the DAC being formed from a plurality of individual segments, the segments being selectively combined to effect the output from the DAC determined by the input and wherein the number of segments is given by 2N?1+x where x is greater or equal to one, and at least one of the segments has a weighting less than that of the least significant bit (LSB) of the overall DAC.

Abstract: Reference signal generators are provided that automatically adjusts a reference signal's amplitude when that signal is delivered into system loads having unknown capacitances. The amplitude is preferably initiated at a maximum amplitude to insure operation of system elements that require the reference signal. It is subsequently adjusted downward to a controlled reference amplitude which is predetermined to be an amplitude sufficient to sustain proper operation of the system elements but sufficiently reduced to minimize the spurious signals typically generated by fast high-level current transitions. In addition, the reduction to the controlled amplitude reduces the system current drain. The level control is realized in a buffer amplifier so that the amplitude level of an oscillator signal can be set independently to maximize its signal-to-noise performance. Accordingly, requirements for the reference amplitude do not compromise requirements for the amplitude level of the oscillator signal.

Abstract: A switched current temperature sensing circuit comprises a BJT arranged to conduct a forced emitter current IE of the form Ifixed+(Ifixed/?), such that the base current is given by Ifixed/? and the collector current is given by Ifixed+(Ifixed/?)?(Ifixed/?)=Ifixed. Base current Ifixed/? is mirrored to the emitter, and a current source provides current Ifixed, which is switched between at least a first value I and a second value N*I such that the BJT's base-emitter voltage has a first value Vbe1 when Ifixed=I and a second value Vbe2 when Ifixed=N*I, such that: ?Vbe12=Vbe1?Vbe2=(nFkT/q)(ln N), where nF is the BJT's emission coefficient, k is Boltzmann's constant, T is absolute temperature, and q is the electron charge.