Abstract: Exemplary semiconductor processing methods may include providing a first etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A first layer of silicon-and-germanium-containing material, a second layer of silicon-and-germanium-containing material, and a layer of silicon-containing material may be disposed on the substrate. The methods may include providing a passivation precursor to the processing region. The methods may include contacting the substrate with the first etchant precursor and the passivation precursor. The contacting may selectively etch the first layer of silicon-and-germanium-containing material. The contacting may form a passivation material on the substrate.

Abstract: The present technology includes methods and systems for forming advanced memory structures, and the resulting devices. Methods include forming a dielectric material layer over a first sidewall, a second sidewall, and a bottom wall, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom wall is disposed between the first sidewall and the second sidewall. Methods include depositing a liner material directly on the dielectric material layer on the first sidewall, the second sidewall, and the bottom wall. Methods include removing at least a portion of the liner material from the bottom wall. Methods include selectively depositing a conductive material on a remaining portion of the liner material.

Abstract: Horizontal gate-all-around devices and methods of manufacturing the same are described. The hGAA devices comprise a self-aligned low-? inner spacer adjacent to the replacement metal gate. The method includes growing the source/drain epitaxial material without an inner spacer and then forming a low-? inner spacer material after dummy gate removal and nanosheet release.

Abstract: Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are described. The methods include forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom on a substrate. The methods further include forming a blocking layer on the bottom by exposing the substrate to a blocking species that comprises a hydrocarbon and at least one additive; selectively depositing a barrier layer on the sidewalls; selectively depositing a metal liner on the barrier layer on the sidewalls; removing the blocking layer; and performing a gap fill process to fill the gap with a gapfill material.

Abstract: Exemplary flip chip packages may include a carrier substrate. The packages may include a chiplet electrically and physically coupled with the carrier substrate via a plurality of interconnects. The packages may include an underfill positioned between the carrier substrate and the chiplet. The packages may include an epoxy molding coupled with the carrier substrate and covering an exposed surface of the chiplet. The packages may include a die attach film layer positioned about the chiplet. The die attach film layer may extend between and separates the chiplet and the carrier substrate. The die attach film layer may extend between and separates the chiplet and the epoxy molding. The die attach film layer may have a coefficient of thermal expansion of between 30 ppm/C and 35 ppm/C, inclusive. The die attach film layer may have a Young's modulus of between 4 GPa and 5 GPa, inclusive.

Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.

Abstract: Embodiments described herein relate to methods of printing double exposure patterns in a lithography environment. The methods include determining a second exposure pattern to be exposed with a first exposure pattern in a lithography process. The second exposure pattern is determined with a rule-based process flow or a lithography model process flow.

Abstract: An endpoint detection system for enhanced spectral data collection is provided. An optical bundle is coupled to a light source. The optical bundle includes an emitting optical fiber and a receiving optical fiber disposed at a pairing angle relative to the emitting optical fiber. The optical bundle is coupled to a collimator assembly that receives a light beam of incident light from the emitting optical fiber and directs spectral components of the light beam to first and second portions of a substrate surface. The collimator collects reflected spectral components produced by the spectral components directed to the substrate surface. The collimator assembly transmits the reflected spectral components to the receiving fiber, which transmits the reflected spectral components to a light detection component. A processing device coupled to the light detection component determines a reflectance of the substrate surface based on the reflected spectral components.

Abstract: In one embodiment, a method is provided for polishing a substrate. The method generally includes receiving a plurality of dwell times of a pad conditioning disk, wherein the plurality of dwell times are to be used in a pad conditioning process performed on a pad disposed on a platen, and each dwell time corresponding to a zone of a plurality of zones of the pad disposed on the platen, determining a plurality of total pad conditioning disk cut times to be used in the pad conditioning process, each total pad conditioning disk cut time corresponding to a zone of the plurality of zones, and generating a first pad wear removal model based on a set of parameters, including the plurality of dwell times and the plurality of total pad conditioning disk cut times.

Abstract: Organometallic precursors and methods of depositing high purity metal films are discussed. Some embodiments utilize a method comprising exposing a substrate surface to an organometallic precursor comprising one or more of molybdenum (Mo), tungsten (W), osmium (Os), technetium (Tc), manganese (Mn), rhenium (Re) or ruthenium (Ru), and an iodine-containing reactant comprising a species having a formula RIx, where R is one or more of a C1-C10 alkyl, C3-C10 cycloalkyl, C2-C10 alkenyl, or C2-C10 alkynyl group, I is an iodine group and x is in a range of 1 to 4 to form a carbon-less iodine-containing metal film. Some embodiments advantageously provide methods of forming metal films having low carbon content (e.g., having greater than or equal to 95% metal species on an atomic basis), without using an oxidizing agent or a reductant.

Abstract: A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

Abstract: Actual physical locations of dies on a substrate package may be identified without using a full metrology scan of the substrate. Instead, one or more cameras may be used to efficiently locate the approximate location of any of the alignment features based on their expected positioning in the design file for the packages are substrate. The cameras may then be moved to locations where alignment features should be, and images may be captured to determine the actual location of the alignment feature. These actual locations of the alignment features may then be used to identify coordinates for the dies, as well as rotations and/or varying heights of the dies on the packages. A difference between the expected location from the design file and the actual physical location may be used to adjust instructions for the digital lithography system to compensate for the misalignment of the dies.

Abstract: Exemplary methods of semiconductor processing include delivering a carbon-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A flowrate ratio of the hydrogen-containing precursor to the carbon-containing precursor may be maintained greater than or about 2:1. The methods include forming a layer of graphene on a substrate positioned within the processing region of the semiconductor processing chamber. The substrate may be maintained at a temperature below or about 600° C.

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Abstract: Embodiments described herein provide for optical devices with methods of forming optical device substrates having at least one area of increased refractive index or scratch resistance. One method includes disposing an etch material on a discrete area of an optical device substrate or an optical device layer, disposing a diffusion material in the discrete area, and removing excess diffusion material to form an optical material in the optical device substrate or the optical device layer having a refractive index greater than or equal to 2.0 or a hardness greater than or equal to 5.5 Mohs.

Abstract: Embodiments disclosed herein include a method of calibrating a processing tool. In an embodiment, the method comprises providing a first substrate with a first emissivity, a second substrate with a second emissivity, and a third substrate with a third emissivity. In an embodiment, the method may include running a recipe on each of the first substrate, the second substrate, and the third substrate, where the recipe includes a set of calibration attributes. In an embodiment, the method may further comprise measuring a layer thickness on each of the first substrate, the second substrate, and the third substrate. In an embodiment, the method further comprises determining if the layer thicknesses are uniform.

Abstract: Embodiments of the present disclosure relate to measurement systems and methods of measuring efficiency of optical devices. In one example, the measurement systems include a light source, a mirror, an illumination source, and a sensor. The light source provides a light beam to the optical device to be diffracted into diffraction beams having diffraction orders. The diffractions beams form a diffraction pattern. The method includes positioning the optical device in the measurement system and directing the diffraction beams to the sensor. The sensor is operable to measure the efficiency of the optical device by measuring the diffraction pattern.

Abstract: A substrate process station includes a housing including a transport region and process region. The process station further includes a magnetic levitation assembly disposed in the transport region configured to levitate and propel a substrate carrier. The magnetic levitation assembly includes a first track segment including first rails disposed in the transport region and below the process region, wherein the first rails each include a first plurality of magnets. The process station further includes a pedestal assembly comprising a pedestal disposed within the housing. The pedestal is moveable between a pedestal transfer position and a process position, wherein the pedestal is disposed between the first rails in the pedestal transfer position to receive a substrate from the substrate carrier, and wherein the pedestal is moveable between the first rails to position the received substrate in the process region in the process position.

Abstract: The present disclosure provides a multi-substrate handling system having an alignment apparatus capable of positioning each of a set of substrates in predetermined orientations for transfer. A buffer chamber is configured to receive and condition the set of substrates which are disposed on a substrate carrier. A first transfer assembly is configured to transfer the set of substrates to and from the buffer chamber and is capable of transferring each of the set of substrates from the alignment apparatus to the carrier in the buffer chamber. The carrier includes a plurality of modules capable of securing the set of substrates. The system includes a second transfer assembly having at least two robots configured to transfer the carrier of the set of substrates between the buffer chamber and a process chamber. The process chamber is capable of processing the set of substrates using different process parameters for each substrate.

Abstract: The present disclosure generally relates to photolithography systems, and methods for correcting positional errors in photolithography systems. When a photolithography system is first started, the system enters a stabilization period. During the stabilization period, positional readings and data, such as temperature, pressure, and humidity data, are collected as the system prints or exposes a substrate. A model is created based on the collected data and the positional readings. The model is then used to estimate errors in subsequent stabilization periods, and the estimated errors are dynamically corrected during the subsequent stabilization periods.