Abstract: Disclosed herein is a method for non-destructive depth-profiling including projecting a pulsed pump beam into a specimen, projecting a pulsed probe beam thereinto, and sensing light returned therefrom to obtain a measured signal. Each probe pulse is configured to undergo Brillouin scattering off a primary acoustic pulse induced by the directly preceding pump pulse, so as to be scattered there off at a respective depth within the specimen. The method further includes executing an optimization algorithm configured to receive as inputs the measured signal, and/or a processed signal obtained therefrom, and output values of structural parameter(s) characterizing the specimen through minimization of a cost function indicative of a difference between the measured signal and a simulated signal obtained using a forward model simulating the scattering of a pulsed probe beam off at least the primary acoustic pulses.

Abstract: Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a flexible membrane coupled with the carrier body. The flexible membrane may include a substrate-receiving surface that faces away from the carrier body. The substrate-receiving surface may include a plurality of gripping elements that protrude away from the substrate-receiving surface. Each of the plurality of gripping elements may have a maximum lateral dimension that is no greater than 2 mm.

Abstract: Exemplary substrate support assemblies may include a support plate that comprises a substrate support surface. The assemblies may include a support stem coupled with the support plate. A channel may be defined through at least a portion of a length of the support stem and extends through the substrate support surface. A temperature sensor assembly may be disposed within the channel. The temperature sensor assembly may include a light pipe disposed within the channel such that a top end of the light pipe extending through at least a portion of the support plate. The temperature sensor assembly may include a sensor that is coupled with a bottom end of the light pipe.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a bottom plate coupled with a bottom surface of the chamber body. The chambers may include a substrate support assembly disposed within the chamber body. The substrate support assembly may include a support plate and a support stem coupled with the support plate. The chambers may include a mounting bracket that couples the support stem with a lower surface of the bottom plate. The chambers may include a plurality of tilt actuators. Each of the tilt actuators may couple the mounting bracket with the lower surface of the bottom plate. Each of the tilt actuators may be operable to adjust a vertical distance between the lower surface of the bottom plate and the mounting bracket at a mounting site of the respective tilt actuator to adjust a planarity of the support plate relative to the bottom plate.

Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Exemplary semiconductor processing systems may include a chamber body having sidewalls and a base. The semiconductor processing systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate. The substrates support may include a shaft coupled with the support plate. The semiconductor processing systems may include a liner positioned within the chamber body and positioned radially outward of a peripheral edge of the support plate. An inner surface of the liner may include an emissivity texture.

Abstract: Methods of semiconductor processing may include forming plasma effluents. The plasma effluents may then contact a carbon-containing hardmask and an oxide cap. The plasma effluents can etch one or more features in the oxide cap through one or more apertures of the carbon-containing hardmask. Etching can create a tapered profile for one or more features in the oxide cap. The one or more features can be characterized by a critical dimension at the bottom of the one or more features. The critical dimension can be less than or about 80% of a width of the one or more apertures.

Abstract: Exemplary semiconductor processing systems may include a chamber body having a bottom plate. The systems may include a substrate support disposed within the chamber body. The substrate support may include a support plate and a shaft. The shaft may include a cooling hub that extends through the bottom plate. The shaft may include a ground shaft that is seated atop the cooling hub. The ground shaft may include a ceramic material. The systems may include an inner isolator coupled with a bottom of the support plate. The inner isolator may define an aperture therethrough that receives the shaft. The systems may include an outer isolator that is seated atop the inner isolator. Each of the inner isolator and the outer isolator may include a ceramic material.

Abstract: Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion energy of less than or about 50 eV, or a combination thereof. Flowing the plasma effluents into a processing region of the semiconductor processing chamber. The microwave applicator includes a resonator body and a plate, where the resonator body is formed from or coated with a first dielectric material and the plate is formed from or coated with a second dielectric material.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

Abstract: Exemplary electroplating systems may include a vessel. The systems may include a head that is configured to hold a substrate. The head may be positionable within an interior of the vessel. The systems may include a spray jet array disposed within the interior of the vessel. The spray jet array may include a plate defining a plurality of apertures through a thickness of the plate. The systems may include at least one fluid pump that is fluidly coupled with an inlet end of each of the plurality of apertures.

Abstract: Embodiments of the present technology may include semiconductor processing methods and systems. Methods and systems may include providing a substrate to a processing region of a semiconductor processing chamber, where the substrate includes one or more alternating pairs of a semiconductor material layer and a sacrificial material layer. Methods include forming one or more vertically extending features through the one or more alternating pairs of semiconductor material layer and sacrificial material layer, forming one or more sidewalls having alternating exposed lateral ends of the semiconductor material and the sacrificial material. Methods include forming a protective material layer over the exposed lateral ends of the semiconductor material layer. Methods include laterally recessing at least a portion of the sacrificial material layer from the one or more vertically extending features and trimming a portion of the semiconductor material layer adjacent to the one or more vertically extending features.

Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing a gapfill material, such as titanium nitride (TiN), in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as FinFETs, GAAs, and the like, with a gapfill material without creating a seam. One or more embodiments include selective deposition processes using a carbon (C) layer in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.

Abstract: Exemplary chemical mechanical cleaning systems may include a carrier head. The systems may include a motor that is coupled with the carrier head. The motor may be operable to rotate the carrier head about a central axis of the carrier head. The systems may include a two-stage downforce actuator that is operable to vertically translate the carrier head and the motor between a raised position and a cleaning position. The downforce actuator may include a first stage that includes a linear actuator that is operable to vertically translate the carrier head between the raised position and at least an upper 50% of a vertical travel distance between the raised and cleaning positions. The downforce actuator may include a second stage that includes an expandable flexure that is operable to vertically translate the carrier head between the cleaning position and no greater than a lower 50% of the vertical distance.

Abstract: A method and apparatus for determining a growth rate on a semiconductor substrate is described herein. The apparatus is an optical sensor, such as an optical growth rate sensor. The optical sensor is positioned in an exhaust of a deposition chamber. The optical sensor is self-heated using one or more internal heating elements, such as a resistive heating element. The internal heating elements are configured to heat a sensor coupon. A film is formed on the sensor coupon by exhaust gases flowed through the exhaust and is correlated to film growth on a substrate within a process volume of the deposition chamber.

Abstract: A method and apparatus for patterning semiconductor materials using tin-based materials as mandrels, hardmasks, and liner materials are provided. One or more implementations of the present disclosure use tin-oxide and/or tin-carbide materials as hardmask materials, mandrel materials, and/or liner material during various patterning applications. Tin-oxide or tin-carbide materials are easy to strip relative to other high selectivity materials like metal oxides (e.g., TiO2, ZrO2, HfO2, Al2O3) to avoid influencing critical dimensions and generate defects. In addition, tin-oxide and tin-carbide have low refractive index, k-value, and are transparent under 663-nm for lithography overlay.

Abstract: Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.

Abstract: The enclosed disclosure relates to a method and apparatus for depositing functionalized nanoparticles within a semiconductor structure in order to create a nano-layer capable of enhancing imaging and contrast, The semiconductor structure can include any type of VNAND structure or 3D structure, The nanoparticles are formed in high-aspect ratio trenches of the structure and form a nano-layer. The functionalized nanoparticles comprise synthesized nanoparticles as well as organic molecules. The organic molecules are chosen to selectively bind to certain nanoparticles and surface materials.