Abstract: Apparatus and method for removing material from the susceptor of a batch processing chamber are described. The apparatus comprises a polishing tool including a rotatable platen positioned above the susceptor. A method comprises contacting material deposited on the susceptor with the rotatable platen to remove the material from the susceptor.

Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.

Abstract: Embodiments disclosed within include a method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, including selectively depositing passivation material over a top surface of a patterned photoresist layer trimming undesired portions of the passivation material, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.

Abstract: Some embodiments include a method of depositing a photoresist onto a substrate in a processing chamber. In an embodiment, the method comprises flowing an oxidant into the processing chamber through a first path in a showerhead, and flowing an organometallic into the processing chamber through a second path in the showerhead. In an embodiment, the first path is isolated from the second path so that the oxidant and the organometallic do not mix within the showerhead. In an embodiment, the method further comprises that the oxidant and the organometallic react in the processing chamber to deposit the photoresist on the substrate.

Abstract: Organometallic precursors and methods of depositing high purity metal films are discussed. Some embodiments utilize a method comprising exposing a substrate surface to an organometallic precursor comprising one or more of molybdenum (Mo), tungsten (W), osmium (Os), technetium (Tc), manganese (Mn), rhenium (Re) or ruthenium (Ru), and an iodine-containing reactant comprising a species having a formula RIx, where R is one or more of a C1-C10 alkyl, C3-C10 cycloalkyl, C2-C10 alkenyl, or C2-C10 alkynyl group, I is an iodine group and x is in a range of 1 to 4 to form a carbon-less iodine-containing metal film. Some embodiments advantageously provide methods of forming metal films having low carbon content (e.g., having greater than or equal to 95% metal species on an atomic basis), without using an oxidizing agent or a reductant.

Abstract: A method includes determining queue times associated with operations of a sequence recipe. The operations are associated with production of substrates in a substrate processing system. The method further includes generating a schedule based on the queue times. The method further includes transmitting the schedule to a controller of the substrate processing system. The controller is to control the substrate processing system to produce the substrates based on the schedule.

Abstract: A direct current (DC) power is supplied to a heating element embedded into a substrate support assembly (SSA). A voltage across the heating element and a current through the heating element is measured as the DC power is supplied to the heating element. A resistance of the heating element is determined based on the measured voltage and current. A temperature measurement for the heating element and/or a zone including the heating element is obtained based on signal(s) of a temperature sensor. A temperature model is updated based on the determined resistance and the obtained temperature measurement. The heating element embedded in the SSA and/or an additional heating element embedded in the SSA or in another SSA is controlled based on the updated temperature model during a substrate process.

Abstract: Exemplary methods of forming a silicon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber and include one or more features. The methods may include generating plasma effluents of the silicon-containing precursor in the processing region. The methods may include depositing a silicon-containing material on a vertically extending portion and a horizontally extending portion of the feature. Methods include soaking the deposited silicon-containing material with a second silicon-containing material.

Abstract: Methods of scaling the thickness of the interfacial layer in electronic devices, such as NMOS transistors and PMOS transistors are described. Some embodiments provide a metal film or a metal nitride film that reduces the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer (e.g., silicon oxide (SiOx)) and the high-? dielectric layer (e.g., hafnium oxide (HfOx)). Some embodiments advantageously include annealing the semiconductor substrate to promote or accelerate the scavenging.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a showerhead positioned atop the body. The chambers may include an electrostatic chuck assembly disposed within the body. The assembly may include a puck that may include a first plate including an electrically insulating material and that defines a substrate support surface. The puck may include a multi-zone heating assembly thermally coupled with the first plate. The puck may include bipolar electrodes. The puck may include a second plate that defines cooling channels. The assembly may include an insulator beneath the second plate. The assembly may include a base plate beneath the insulator. The assembly may include a shaft that may include a heater rod coupled with the heating assembly. The shaft may include a cooling fluid lumen fluidly coupled with the cooling channels. The shaft may include a power rod electrically coupled with a bipolar electrode.

Abstract: The present technology includes vertical cell array transistor (VCAAT) with improved floating body effect. The arrays one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source/drain region has a first section adjacent to a source/drain junction and a second section adjacent to a channel body, where the first section has a doping concentration that greater than a doping concentration of the second section.

Abstract: Embodiments of the disclosure relate to methods using an oligomer film to protect a substrate surface. The oligomer film is formed on the substrate surface with a first feature and a second feature each having a feature depth. The first feature has a first critical dimension (CD) and the second feature has a second CD. The semiconductor substrate surface is exposed to one or more monomers to form the oligomer film, and the oligomer film forms selectively on the bottom and fills a portion of the feature depth. The oligomer film fills the feature depth to substantially the same or the same height in each of the first feature and the second feature. Methods of forming semiconductor devices using the oligomer film are also disclosed.

Abstract: Showerhead assemblies for semiconductor manufacturing processing chambers and semiconductor manufacturing processing chambers using the showerhead assemblies are described. The showerhead assemblies comprise a backing plate with an embedded heater and a faceplate. The embedded heater has a radius sufficient to located the heater over a sidewall of the processing chamber and reduces temperature non-uniformity of a wafer during processing.

Abstract: Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The system may include a substrate support extending through the base of the chamber body. The chamber body may define an access circumferentially extending about the substrate support at the base of the chamber body. The system may include one or more isolators disposed within the chamber body. The one or more isolators may define an exhaust path between the one or more isolators and the chamber body. The exhaust path may extend to the base of the chamber body. The systems may include a fluid source fluidly coupled with the chamber body at the access extending about the substrate support.

Abstract: Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer?2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.

Abstract: Apparatus and methods for cooling down a susceptor assembly are described. A heat exchange passage in a susceptor assembly thermal break transfers heat from processing gases that flow through the susceptor assembly to a cooling jacket and cools down the susceptor assembly and associated hardware.

Abstract: Substrate support assemblies may include an electrostatic chuck body defining a substrate support surface that defines a substrate seat. Assemblies may include a support stem coupled with the electrostatic chuck body. Assemblies may include a first bipolar electrode embedded within the electrostatic chuck body. Assemblies may include a second bipolar electrode embedded within the electrostatic chuck body radially inward of at least a portion of the first bipolar electrode and coaxial with the first bipolar electrode. Assemblies may include an annular electrode disposed about the first bipolar electrode, where the annular electrode is DC floated and RF powered and exhibits an induced DC current.

Abstract: Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a substrate support assembly disposed within the chamber body. The chambers may include a substrate support assembly having a support plate seated atop a support stem. The chambers may include a radio frequency (RF) shield seated atop the chamber body and extending about a peripheral edge of the support plate. The RF shield may include a lower annular member. The RF shield may include an upper annular member seated atop the lower annular member. The upper annular member may define a lip that protrudes radially outward from an outer surface of the upper annular member. Each of the lower annular member and the upper annular member may include a dielectric material.

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided that are particularly suited for polishing substrates utilized in hybrid bonding applications. Methods and articles may include a plurality of first polishing elements, where at least one of the plurality of first polymer layers forms the polishing surface; and one or more second polishing elements, where at least a region of each of the one or more second polishing elements is disposed between at least one of the plurality of first polishing elements and a supporting surface of the polishing pad. One or more first polishing elements have a Shore D hardness of greater than 60, one or more second polishing elements have a Shore D hardness of from about 20 to less than 60, and the polishing article has a total Shore D hardness of greater than or about 50.

Abstract: Exemplary methods and systems of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. Methods may include forming a low quality oxide within one or more of the recesses, where the low quality oxide and a silicon-containing material each contain an exposed surface. Methods include contacting the low quality oxide and the high quality semiconductor material with a passivating agent selective to a surface defect of the low quality oxide. Methods include contacting the substrate with an etching agent and/or a cleaning agent, where the contacting with the cleaning agent removes the high quality semiconductor material at an equal or faster rate than the low quality oxide.