Abstract: Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heating assembly. The substrate support assembly comprises a body having a substrate support surface and a lower surface, one or more main resistive heaters disposed in the body, a plurality of spatially tunable heaters disposed in the body, and a spatially tunable heater controller coupled to the plurality of spatially tunable heaters, the spatially tunable heater controller configured to independently control an output one of the plurality of spatially tunable heaters relative to another of the plurality of spatially tunable heaters.

Abstract: A method including receiving, by a processing device, image data characterizing light reflected from of a film disposed on a processed surface of a substrate. The image data corresponds to one or more locations across a surface of the film and indicates a camera perspective angle associated with capturing the image data. The method further includes determining, by the processing device using the image data, reflection data indicating reflection effect of the light reflected from the film. The method further includes processing the reflection data using one or more machine-learning model (MLMs). The method further includes determining one or more process result metrics of the film corresponding to the one or more locations. The method may further includes preparing the one or more process result metrics for display on a graphical user interface (GUI). The method may further include preparing the one or more process result metrics for processing in a script-based environment.

Abstract: Embodiments of the present disclosure generally relate to a cryogenic micro-zone connection assembly for a substrate support assembly suitable for use in cryogenic applications. In one or more embodiments, the cryogenic micro-zone connection assembly has a first end having a micro-zone connector. A second end has a socket connection. A flange is disposed between the micro-zone connector and the socket connection. And a wiring harness is coupled at the first end to the micro-zone connector, extends through the flange and is coupled at the second end to the socket connection.

Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.

Abstract: Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

Abstract: Disclosed herein are systems and methods relating to a transfer chamber for an electronic device processing system. The transfer chamber can include a first magnetic levitation track having a face-up orientation and a second magnetic levitation track spaced from the first magnetic levitation track and having a face-down orientation. The system can include substrate carriers that move along the first and second magnetic levitation tracks where each substrate carrier includes a magnet on a bottom portion to interact with a first magnetic field and a second magnet on a top portion to interact with a second magnetic field. The system also can include at least one lift pin assembly to move the substrate carriers in a vertical direction between the first and second magnetic levitation tracks.

Abstract: Methods for depositing molybdenum-containing films on a semiconductor substrate are described. The substrate is exposed to a bis(arene)molybdenum (0) precursor and a halide-free reactant to form the molybdenum-containing film (e.g., molybdenum metal (elemental molybdenum), molybdenum carbide, molybdenum carbonitride, molybdenum silicide, molybdenum carbosilicide, molybdenum sulfide, molybdenum carbosulfide, molybdenum nitride, molybdenum phosphide, or molybdenum carbophosphide. The exposures can be sequential or simultaneous.

Abstract: Methods of depositing thin films of hafnium oxide possessing strong ferroelectric properties are described. A hafnium oxide monolayer is formed in a first process cycle comprising sequential exposure of a substrate to a hafnium precursor, purge gas, first oxidant and purge gas. A doped hafnium oxide monolayer is formed in a second process cycle comprising sequential exposure of the substrate to a hafnium precursor, purge gas, dopant precursor, purge gas, second oxidant and purge gas. Thin films of hafnium oxide are also described.

Abstract: Embodiments herein are directed to localized wafer thickness correction. In some embodiments, a method may include providing a substrate including an upper surface having a raised portion extending above a plane defined by the upper surface, and a non-raised portion adjacent the raised portion. The method may further include performing a metrology scan of the upper surface to determine a first dimension of the raised portion and a second dimension of the non-raised portion, and depositing a hardmask over the upper surface, including over the raised portion and the non-raised portion. The method may further include directing ions to the hardmask, wherein a first dose of the ions over the raised portion is greater than a second dose of the ions over the non-raised portion, and performing a first etch to the hardmask to remove the hardmask over the raised portion, wherein the hardmask remains over the non-raised portion.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Abstract: A gapfill precursor may be provided to a processing chamber for filling features in a semiconductor structure. The features may have different critical dimensions. An etchant configured to etch the gapfill material may also be provided with the precursor. A plasma power in the chamber may have a duty cycle of a first RF power provided during a first time duration and a second RF power provided during a second time duration, where the second RF power is less than the first RF power. The RF power levels may be selected such that the gapfill material is deposited in the bottom of the features while being etched at a top of the features during the first time, and deposited on both the bottom and top of the features during the second time, where the features having different CDs finish the gapfill process at about the same time.

Abstract: Gas distribution apparatus comprising a backing plate and faceplate, and methods of use are described. The backing plate has a peripheral channel with a plurality of inwardly angled inlet channels extending from the peripheral channel to the front surface of the backing plate. The plurality of inwardly angled inlet channels are located in an inlet semicircle of the backing plate and spaced to form an inlet zone comprising a minor arc of a semicircle less than 160°. An outlet opening in an outlet semicircle in the range of 30° to 90° is centered opposite the center of the minor arc of the inlet semicircle.

Abstract: Apparatus and methods for controlling plasma profiles during PVD deposition processes are disclosed. Some embodiments utilize EM coils placed above the target to control the plasma profile during deposition.

Abstract: Technologies directed to cooling flow according to predicted cooling parameters for substrate processing are described. In some embodiments, a method includes receiving first data indicative of a process recipe for processing a substrate in a processing chamber of a substrate processing system. The method further includes inputting the first data into a model. The model includes a digital twin configured to represent thermal characteristics of the processing chamber. The method further includes receiving, via the model, a predicted value of a parameter associated with a flow of coolant through a cooling loop of the processing chamber. The method further includes causing coolant to flow through the cooling loop based on the predicted value of the parameter during execution of the process recipe in the processing chamber.

Abstract: Aspects of the present disclosure generally relate to a digital lithography system and methods for alignment resolution with the digital lithography system. The digital lithography system includes a metrology system configured to improve overlay alignment for different layers of the lithography process. The metrology system includes an inline metrology system (IMS) in combination with an on tool metrology system (OTM), which enable substrate overlay alignment and die placement correction. The inline metrology system may be positioned on an inline metrology tool and the on tool metrology system is positioned on a digital lithography tool. The inline metrology system facilitates measurement of high-throughput measurement inline metrology data for marks such as die marks and global alignment marks for verification of process stability and die placement data for digital data correction. This inline metrology data can be compared with a design file to determine offsets for the digital data correction.

Abstract: Systems and methods for grip-based transport speeds for objects transported at a manufacturing system is provided. A controller can detect an object placed on an end effector of a robot arm. The controller can apply vacuum pressure to secure the object to the end effector via vacuum grip pads. The controller can obtain a vacuum pressure measurement indicating the amount of vacuum pressure between the object and the end effector and determine whether the obtained vacuum pressure measurement satisfies a vacuum pressure criterion. The controller can determine a transport speed setting for transporting the object using the robot arm based on whether the obtained vacuum pressure measurement satisfies the vacuum pressure criterion. The controller can cause the robot arm to move the object according to the transport speed setting.

Abstract: Hard masks and methods of forming hard masks are described. The hard mask has an average roughness less than 10 nm and a modulus greater than or equal to 400 GPa. The method comprises exposing a substrate to a deposition gas comprising a dopant gas or a precursor (solid (e.g. Alkylborane compounds) or liquid (e.g. Borazine)), a carbon gas and argon at a temperature less than or equal to 550 C, and igniting a plasma from the deposition gas to form an ultrananocrystalline diamond film having an average roughness less than 10 nm and a modulus greater than or equal to 400 GPa.

Abstract: Methods for depositing film comprising cyclical exposure of a substrate surface to a precursor and a degas environment to remove gas evolved from the film. Some embodiments further comprise the incorporation poisoning the top of a feature to inhibit film growth at the top of the feature. Some embodiments further comprising etching a portion of the film deposited at the top of a feature between cycles to increase gap-fill uniformity.

Abstract: Embodiments described herein relate to chamber component cleaning systems and methods for cleaning a chamber component. The chamber component cleaning system includes a spray station, at least a first cleaning station, a dry station, a component transfer mechanism, and one or more enclosures that enclose the spray station, at least the first cleaning station, the dry station, and the component transfer mechanism. The spray station has a holder to position a chamber component in a path of a flow of a cleaning spray and a movable nozzle to provide the flow of the cleaning spray at a first pressure in a path of portions of the chamber component. The first cleaning station has a push mechanism to force a cleaning fluid through features and/or holes of the chamber component and at least one movable transducer to provide ultrasonic energy to the portions of the chamber component.

Abstract: Exemplary semiconductor processing methods may include depositing a first material on a first substrate. The first material may be characterized by a first average surface roughness greater than 5 ?. The methods may include depositing a fill material on the first material. The methods may include planarizing the fill material to form a planarized fill material. The planarized fill material may be characterized by a second average surface roughness less than the first average surface roughness. The methods may include bonding the planarized fill material to a second substrate.