Abstract: Disclosed herein are approaches for using angle control of deposition plus etch processes to enable 2D and/or 3D device patterning. In one approach, a method may include providing a substrate including a plurality of trenches having different dimensions, and depositing a film atop the substrate. The film may be delivered at a non-zero angle relative to a perpendicular extending from a top surface of the substrate, wherein an amount of the film formed along a bottom surface of a first trench is greater than an amount of the film formed along a bottom surface of a second trench. The method may further include delivering ions into the substrate in a reactive ion etching process to remove material from at least one of: the first sidewall of the first trench, the bottom surface of the second trench, and the film.

Abstract: A method includes receiving trace sensor data associated with a first manufacturing process of a processing chamber. The method further includes processing the trace sensor data using one or more trained machine learning models that generate a representation of the trace sensor data, and then generate reconstructed sensor data based on the representation of the trace sensor data. The method further includes comparing the trace sensor data to the reconstructed sensor data. The method further includes determining one or more differences between the reconstructed sensor data and the trace sensor data. The method further includes determining whether to recommend a corrective action associated with the processing chamber based on the one or more differences between the trace sensor data and the reconstructed sensor data.

Abstract: A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.

Abstract: Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool. In an embodiment, the method comprises measuring a voltage and a current of a transmission line, converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal, calculating a u-vector from the digital voltage signal and the digital current signal, calculating a C1 position of a first capacitor with real components of the u-vector, and calculating a C2 position of a second capacitor with imaginary components of the u-vector.

Abstract: A chemical mechanical polishing system includes a platen to support a polishing pad having a polishing surface, a conduit having an inlet to be coupled to a gas source, and a dispenser coupled to the conduit and having a convergent-divergent nozzle suspended over the platen to direct gas from the gas source onto the polishing surface of the polishing pad.

Abstract: Exemplary modular gas blocks may include a body having inlet and outlet ends. The body may define a portion of a first gas path along a length of the body and may define a second gas path along a width of the body. The first gas path may include channel segments defined within the body. The inlet end may define a gas inlet that is coupled with the first gas path. The body may define first fluid ports that are coupled with the first gas path. A fluid port of the first fluid ports may be coupled with the gas inlet. The first fluid ports may be coupled with one another via a respective channel segment. An upper surface may define a lateral fluid port that is spaced apart from a first fluid port along the width and is coupled with the first fluid port via the second gas path.

Abstract: Embodiments described herein relate to flat optical devices and encapsulation materials for flat optical devices. One or more embodiments include a substrate having a first arrangement of a first plurality of pillars formed thereon. The first arrangement of the first plurality of pillars includes pillars having a height h and a lateral distance d. The first arrangement of the first plurality of pillars includes a gap g corresponding to a distance between adjacent pillars of the first plurality of pillars. An aspect ratio of the gap g to the height h is between about 1:1 and about 1:20. A first adhesion-promoting material is disposed over the first arrangement of the first plurality of pillars. A first encapsulation layer is disposed over the first adhesion-promoting material. The first encapsulation layer fills the gap g between adjacent pillars of the first plurality of pillars. The first encapsulation layer includes a fluoropolymer.

Abstract: Semiconductor components and systems having substrate contacting surfaces with a reduced hardness are provided. Systems and components include a ceramic, metallic, or non-metallic component for contacting a substrate. Systems and components include a layer of coating material on at least a portion of a substrate contacting surface of the component. Systems and components include where the component for contacting a substrate includes a component Vickers hardness value, and the layer of coating material exhibits a coating layer Vickers hardness value. Systems and components include where the coating layer Vickers hardness value is greater than or about 10% less than the component Vickers hardness value.

Abstract: Processing chambers, substrate supports, centering wafers and methods of center calibrating wafer hand-off are described. A centering wafer comprises a disc-shaped body having a top surface and a bottom surface defining a thickness, a center, an outer edge having an outer peripheral face, a first arc-shaped slit and a second arc-shaped slit. Embodiments of the disclosure advantageously provide the ability to use the centering wafer to monitor and control backside pressure and thereby determine the center of a substrate support prior to processing the centering wafer. The centering wafer may be centered at a plurality of different angles by rotating the centering wafer.

Abstract: A vibrating actuator adapted to be installed within a component of an ion implanter, the vibrating actuator including a housing defining an internal cavity, and a vibrating mechanism disposed within the internal cavity, the vibrating mechanism including an actuating element and a vibratory element coupled to the actuating element, wherein when an electrical signal is applied to the actuating element, the actuating element moves the vibratory element to vibrate the housing.

Abstract: A chemical mechanical polishing apparatus includes a platen to hold a polishing pad, a carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, and a temperature control system including a source of a fluid medium and one or more openings positioned over the platen and separated from the polishing pad and configured for the fluid medium to flow onto the polishing pad to heat or cool the polishing pad.

Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing the substrate surfaces to a blocking compound to selectively form a blocking layer on at least a portion of the first surface over the second surface. The substrate is sequentially exposed to a metal precursor with a kinetic diameter in excess of 21 angstroms and a reactant to selectively form a metal-containing layer on the second surface over the blocking layer or the first surface. The relatively larger metal precursors of some embodiments allow for the use of blocking layers with gaps or voids without the loss of selectivity.

Abstract: A method and apparatus for spatially switching radio frequency (RF) power from a single RF power generator to a selected one of two or more impedance matching networks coupled to associated RF electrodes for forming plasma in a plasma chamber. Full RF power may be switched within microseconds to the selected one of the two or more impedance matching networks. The two or more impedance matching networks may be coupled to one or more plasma generating electrodes. The two or more impedance matching networks may be interleaved during plasma processing recipe operation. Impedance matching networks can alternate back and forth during operation of a plasma processing recipe. This interleaving in operation and impedance transformation capabilities may also be performed with more than two impedance matching networks, and may be beneficial in enabling the use of fixed tuned impedance matching networks instead of requiring variable impedance matching networks having variable tuning capabilities.

Abstract: In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

Abstract: A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.

Abstract: Chemical deliver conduits, systems for substrate processing and methods for supplying a chemical to a substrate processing chamber are described. The conduit has a length and connects a vessel containing the chemical to the substrate processing chamber. The conduit comprises an outer channel surrounding an inner channel. The outer channel is in fluid communication with source of a heat transfer fluid, and the inner channel is in fluid communication with the vessel containing the chemical.

Abstract: Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.

Abstract: Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.

Abstract: Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.