Abstract: Embodiments herein generally relate to chemical mechanical polishing (CMP) systems used in the manufacturing of electronic devices. In one embodiment, a substrate carrier for polishing a surface of a substrate includes a retaining ring configured to surround a substrate during a polishing process. The retaining ring includes a first surface that is configured to contact a surface of a polishing pad during the polishing process, a second surface that is on a side of the retaining ring that is opposite to the first surface, and an array of recesses formed in the second surface.

Abstract: Embodiments described herein relate to flat optical devices and methods of forming flat optical devices. One embodiment includes a substrate having a first arrangement of a first plurality of pillars formed thereon. The first arrangement of the first plurality of pillars includes pillars having a height h and a lateral distance d, and a gap g corresponding to a distance between adjacent pillars of the first plurality of pillars. An aspect ratio of the gap g to the height h is between about 1:1 and about 1:20. A first encapsulation layer is disposed over the first arrangement of the first plurality of pillars. The first encapsulation layer has a refractive index of about 1.0 to about 1.5. The first encapsulation layer, the substrate, and each of the pillars of the first arrangement define a first space therebetween. The first space has a refractive index of about 1.0 to about 1.5.

Abstract: Approaches herein provide devices and methods for forming gate-all-around transistors with improved gate spacer k-values. One method may include forming a gate-all-around (GAA) stack including a plurality of alternating first layers and second layers, and forming a source/drain (S/D) cavity through the plurality of alternating first layers and second layers. The method may further include forming an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and second layers, performing a first implant by directing fluorine ions to the GAA stack, through the S/D cavity, wherein the first implant is performed at a temperature greater than 30° Celsius and forming a S/D material in the S/D cavity following the first implant.

Abstract: Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.

Abstract: Disclosed herein is a processing system. The processing system has an upper chamber body and a lower chamber body defining a processing environment. An upper heater is moveably disposed in the upper chamber body. The upper heater has a moveable support and an upper step formed along an outer perimeter. A lower showerhead is fixedly disposed in the lower chamber body. The lower showerhead includes a top surface configured to support a substrate, a lower step disposed along an outer perimeter wherein the substrate is configured to extend from the top surface partially over the lower step. Lift pins are disposed in the lower showerhead and configured to extend through the top surface and support the substrate thereon. Gas holes are disposed in a first zone along the top surface and a second zone on the step and configured to independently flow both a process and non-process gas.

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.

Abstract: A method of analyzing completion of seasoning of semiconductor processing chambers may include training a model using seasoning cycle characteristics data obtained from existing semiconductor processing chambers. A supervised learning process may label the characteristics data based on expert determined identify seasoning completion and may optionally label the characteristics data based on chamber open event information or preventive maintenance information. The trained model may be used to characterize another chamber during seasoning to determine whether seasoning is completed and/or when or how long or how many seasoning cycles may be performed until seasoning is complete.

Abstract: A flow apparatus and process chamber having the same are described herein. In one example, flow apparatus for use in semiconductor processing comprises an inject assembly and an inductive heater coupled to the inject assembly. The inject assembly comprises an inject body, a first gas inlet configured to flow a first gas through the inject body, and a plurality of flow channels disposed in the inject body, the plurality of flow channels coupled to the first gas inlet. The inductive heater is configured to heat a gas and comprises a heater housing, a graphite rod disposed in the heater housing, the graphite rod having a distal end and proximate end, an inductive coil disposed around the graphite rod, and a second gas inlet configured to flow a second gas between the heater housing and a graphite rod.

Abstract: Gas distribution assemblies, processing chambers, and methods for processing substrates are provided. A substrate processing chamber includes a chamber body having a first end and a second end, a lid coupled to the first end of the chamber body, an isolator disposed on an upper surface of the lid, a faceplate disposed on an upper surface of the isolator, a substrate support disposed on a shaft extending through the second end of the chamber body, a pumping ring positioned within the chamber body, and an exhaust outlet in fluid communication with a system foreline and the plurality of apertures. The processing chamber defines a processing region between the substrate support and the faceplate. The pumping ring includes a flange extending in a plane generally parallel with a top surface of the substrate support that defines a plurality of apertures.

Abstract: Exemplary semiconductor processing methods may include performing a pre-treatment on a substrate housed within a processing region of a semiconductor processing chamber. The substrate may include a layer of silicon-and-carbon-containing material. The pre-treatment may remove native oxide or residue from a surface of the layer of silicon-and-carbon-containing material. The methods may include providing a silicon-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the silicon-containing precursor. The contacting may deposit a layer of silicon-containing material on the layer of silicon-and-carbon-containing material. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the oxygen-containing precursor.

Abstract: Gas distribution assemblies for semiconductor devices are described. The gas distribution assemblies include a backplate, a faceplate, a counterbored hole, and at least one orifice. The at least one orifice includes, for example, at least one straight orifice, or at least two angled orifices. Some embodiments of the gas distribution assemblies provide for reduced plasma damage in a processing chamber. Some embodiments of the gas distribution assemblies provide for reduced jetting on a substrate in a processing chamber. Methods of reducing plasma damage in gas distribution assemblies are also described.

Abstract: A processing chamber and port adaptor are provided. Processing chambers include a chamber body having a lid coupled to the first end of the chamber body, a gas ring adjacent the first end of the chamber body, and a substrate support, where a processing region is defined between the substrate support and the lid. The processing chamber includes a port adapter coupled to the second end of the chamber body. The port adapter includes a body defining a plurality of apertures in fluid communication with the processing region, where each of the apertures are spaced apart along the body such that a distance between adjacent apertures is within about 20% of an average aperture spacing distance, an individually controllable valve fluidly coupled to one or more of the plurality of apertures, and an exhaust system in fluid communication with a system foreline and the plurality of apertures.

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. One or more groups of layers are formed on top of the substrate. A compensation layer is formed on top of at least one group of layers. At least one silicon layer is formed on top of the compensation layer. At least a portion of one or more layers in the one or more groups of layers is etched. The semiconductor device is formed.

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. The methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.

Abstract: Embodiments of the present disclosure generally relate to optical devices. More specifically, embodiments described herein relate to optical devices and methods of manufacturing a patterned optical device film on an optical device substrate. According to certain embodiments, an inkjet deposition process is used to deposit a patterned inkjet coating layer on the optical device substrate. A deposition process may then be used to deposit an optical device material on the patterned inkjet coating and the optical device substrate. The patterned inkjet coating on the optical device substrate may then be washed with an appropriate detergent to lift-off the patterned inkjet coating layer from the optical device substrate to form the patterned optical device film.

Abstract: Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The system may include a substrate support extending through the base of the chamber body. The chamber body may define an access circumferentially extending about the substrate support at the base of the chamber body. The system may include one or more isolators disposed within the chamber body. The one or more isolators may define an exhaust path between the one or more isolators and the chamber body. The exhaust path may extend to the base of the chamber body. The systems may include a fluid source fluidly coupled with the chamber body at the access extending about the substrate support.

Abstract: Disclosed herein is a rare-earth oxide coating on a surface of an article with one or more interruption layers to control crystal growth and methods of its formation. The coating may be deposited by atomic layer deposition and/or by chemical vapor deposition. The rare-earth oxides in the coatings disclosed herein may have an atomic crystalline phase that is different from the atomic crystalline phase or the amorphous phase of the one or more interruption layers.

Abstract: Certain aspects of the present disclosure provide techniques for automatically detecting and classifying tumor regions in a tissue slide. The method generally includes obtaining a digitized tissue slide from a tissue slide database and determining, based on output from a tissue classification module, a type of tissue of shown in the digitized tissue slide. The method further includes determining, based on output from a tumor classification model for the type of tissue, a region of interest (ROI) of the digitized tissue slide and generating a classified slide showing the ROI of the digitized tissue slide and an estimated diameter of the ROI. The method further includes displaying on an image display unit, the classified slide and user interface (UI) elements enabling a pathologist to enter input related to the classified slide.

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.