Abstract: Embodiments of packaged chamber components and methods of packaging chamber components are provided herein. In some embodiments, a packaged chamber component for use in a process chamber includes: an insert having an annular trench disposed about a raised inner portion, wherein the annular trench is disposed between the raised inner portion and an outer lip, wherein a ledge couples the raised inner portion to the outer lip, wherein the ledge includes a first portion and a second portion disposed radially outward of the first portion, and wherein the second portion includes a resting surface that extends upward and radially outward of an upper surface of the first portion; and a chamber component disposed in the annular trench of the insert and supported by the resting surface such that one or more critical surfaces of the chamber component are spaced apart from the insert.

Abstract: One or more embodiments described herein generally relate to methods for chucking and de-chucking a substrate to/from an electrostatic chuck used in a semiconductor processing system. Generally, in embodiments described herein, the method includes: (1) applying a first voltage from a direct current (DC) power source to an electrode disposed within a pedestal; (2) introducing process gases into a process chamber; (3) applying power from a radio frequency (RF) power source to a showerhead; (4) performing a process on the substrate; (5) stopping application of the RF power; (6) removing the process gases from the process chamber; and (7) stopping applying the DC power.

Abstract: Embodiments described herein generally relate to porous plugs having sealing layers for use in substrate support pedestals and methods for forming the same. In one or more embodiments, the sealing layer can be formed in-situ by applying a fluoroelastomer composition to at least one of the porous plug and the walls of a cavity of an electrostatic chuck. The fluoroelastomer composition can be cured in-situ to form the sealing layer between the porous plug and the wall of the cavity. The porous plug is positioned within the cavity to control the flow of gas through a gas flow passage. The sealing layer is positioned adjacent to the porous plug and is capable of forming one or more of a radial seal between the porous plug and the wall of the cavity and an axial seal between the porous plug and a cooling base.

Abstract: A system includes a radiation source configured to emit a radiation beam. The system further includes a first optical sensor configured to detect a first intensity of a first portion of the radiation beam reflected from a surface of an object. The system further includes a second optical sensor configured to detect a second intensity of a second portion of the radiation beam scattered by the surface of the object. The system further includes a processing device communicatively coupled to the first optical sensor and the second optical sensor. The processing device is configured to determine at least one of a roughness or an emissivity of the surface of the object based on a comparison of the first intensity and the second intensity.

Abstract: Exemplary methods of OLED device processing are described. The methods may include forming an anode on a substrate. Forming the anode may include forming a first metal oxide material on the substrate, forming a metal layer over the first metal oxide material, forming a protective barrier over the metal layer, and forming a second metal oxide material over the amorphous protection material. The protective barrier may be an amorphous protection material overlying the metal layer.

Abstract: Embodiments of the present disclosure generally relate to lift pins and to apparatus for controlling lift pin movement. In an embodiment, an apparatus for positioning a substrate in a chamber is provided. The apparatus includes a chamber component, a lift pin having a top surface for supporting the substrate and a lift pin shaft and a stopper. The apparatus further includes a compressible element positioned between the chamber component and the stopper, the compressible element further positioned around the lift pin shaft, the lift pin being moveable relative to a substrate transfer plane by movement of a substrate support in contact with the compressible element.

Abstract: A method and circuit for performing vector operations may include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the operation to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector operation.

Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a bi-metallic silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The bi-metallic silicide layer includes a first metal, a second metal different than the first metal, and a silicon containing compound, and includes greater than or about 0.8 E+14 per cm?2 second metal atoms. The first metal layer includes the first metal and overlies the bi-metallic silicide layer.

Abstract: A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors that are arranged in a honeycomb pattern to maximize the available capacitor footprint on top of the memory array. The bit lines may partially intersect with bottom source/drain regions of two adjacent columns of the vertical transistors, where the columns may be offset based on the honeycomb pattern. The word lines may have a varying width that increases as the word lines enclose the gate regions of the transistors and that decreases between adjacent transistors. The transistor stages may each be formed individually and incrementally, with the bottom source/drain region and the bit lines being completed first, followed by the gate region and the word lines, followed by the top source/drain regions and the capacitors.

Abstract: Exemplary semiconductor component assembly platforms include a base frame having a frame body extending from a first end to a second end. The component assembly platforms include a telescoping frame movably connected to the base frame and a component support movably connected to the telescoping frame. Semiconductor component assembly platforms exhibit a compressed position and a fully extended position. In a compressed position, a first end of the telescoping frame is disposed substantially above a first end of the base frame. In an extended position, the first end of the telescoping frame is disposed between the first end and the second end of the base frame, and a second end of the component support is disposed outward of the second end of the telescoping frame. The component assembly platform may be characterized by having a fully extended length that is at least about 1.2 times greater than the compressed length.

Abstract: Exemplary methods for detecting substrate slippage include sweeping a first sensor and a second sensor of an in-situ monitoring system across the substrate as the substrate undergoes polishing with a rotatable platen. A first sequence of signal values from the first sensor and a second sequence of signal values from the second sensor include a signal strength relative to the thickness of the layer. For each signal value of at least some of the first sequence of signal values and second sequence of signal values, the method may include determining a first and second position on the substrate respective. The method may also include activating a slippage alert if: the signal strength varies by 30% or more from the first sequence of signal values to the second sequence of signal values, a position on the substrate for the second signal value cannot be determined, or a combination thereof.

Abstract: Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack is provided and includes a silicon oxide layer disposed on a workpiece, a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer. The hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

Abstract: A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.

Abstract: An apparatus may include a drift tube assembly having a plurality of drift tubes to conduct an ion beam along a beam propagation direction. The plurality of drift tubes may define a multi-gap configuration corresponding to a plurality of acceleration gaps, wherein at least one powered drift tube of the drift tube assembly is coupled to receive an RF voltage signal. The apparatus may also include a DC electrode assembly that includes a conductor line, arranged within a resonator coil that is coupled to receive a DC voltage signal into the at least one powered drift tube. The DC electrode assembly may also include a DC electrode arrangement, connected to the conductor line and disposed within the at least one powered drift tube.

Abstract: A method of training a neural network includes obtaining two ground truth thickness profiles a test substrate, obtaining two thickness profiles for the test substrate as measured by an in-situ monitoring system while the test substrate is on polishing pads of different thicknesses, generating an estimated thickness profile for another thickness value that is between the two thickness values by interpolating between the two profiles, and training a neural network using the estimated thickness profile.

Abstract: A method of fabricating a device including a superconductive layer includes depositing a seed layer on a substrate, exposing the seed layer to an oxygen-containing gas or plasma to form a modified seed layer, and after exposing the seed layer to the oxygen-containing gas or plasma depositing a metal nitride superconductive layer directly on the modified seed layer. The seed layer is a nitride of a first metal, and the superconductive layer is a nitride of a different second metal.

Abstract: Methods of forming optical devices using nanoimprint lithography and etch processes are provided. In one embodiment, a method is provided that includes depositing a first resist layer on a substrate, the substrate having a hardmask disposed thereon, imprinting a first resist portion of the first resist layer with a first single-height stamp, etching the first resist portion of the first resist layer, etching a first hardmask portion of the hardmask corresponding to the first resist portion of the first resist layer, removing the first resist layer and depositing a second resist layer, imprinting a second resist portion of the second resist layer with a second single-height stamp, etching the second resist portion of the second resist layer, and etching a second hardmask portion of the hardmask corresponding to the second resist portion of the second resist layer.

Abstract: Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body, across the substrate, and to an upper gas outlet on a second side of the chamber body, flowing a purge gas from a lower gas inlet on the first side of the chamber body, across the lower surface of the susceptor, and to a lower gas outlet on the second side of the chamber body, and maintaining a pressure of the lower chamber region greater than a pressure of the upper chamber region.