Abstract: Exemplary substrate processing systems may include a transfer region housing defining a transfer region, and including substrate supports and a transfer apparatus. The transfer apparatus may include a central hub having a housing, and including a first shaft and a second shaft. The housing may be coupled with the second shaft, and may define an internal housing volume. The transfer apparatus may include a plurality of arms equal to a number of substrate supports of the plurality of substrate supports. Each arm of the plurality of arms may be coupled about an exterior of the housing. The transfer apparatus may include a plurality of arm hubs disposed within the internal housing volume. Each arm hub of the plurality of arm hubs may be coupled with an arm of the plurality of arms through the housing. The arm hubs may be coupled with the first shaft of the central hub.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. Subsequent to patterning the mask, a breakthrough treatment is performed, the breakthrough treatment comprising a first physical bombardment operation, a second iterative isotropic and directional plasma etch operation, and a third directional breakthrough operation. Subsequent to performing the breakthrough treatment, the semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A processing tool for a plasma process includes a chamber body that has an interior space that provides a plasma chamber and that has a ceiling and an opening on a side opposite the ceiling, a workpiece support to hold a workpiece such that at least a portion of a front surface of the workpiece faces the opening, an actuator to generate relative motion between the chamber body and the workpiece support such that the opening moves laterally across the workpiece, a gas distributor to deliver a processing gas to the plasma chamber, an electrode assembly comprising a plurality of coplanar filaments extending laterally through the plasma chamber between the workpiece support and the ceiling, each of the plurality of filaments including a conductor, and a first RF power source to supply a first RF power to the conductors of the electrode assembly to form a plasma.

Abstract: Exemplary semiconductor processing systems include a processing chamber defining a processing region. The semiconductor processing systems may include a foreline coupled with the processing chamber. The foreline may define a fluid conduit. The semiconductor processing systems may include a foreline trap coupled with a distal end of the foreline. The semiconductor processing systems may include a removable insert provided within an interior of the foreline trap. The semiconductor processing systems may include a throttle valve coupled with the foreline trap downstream of the removable insert.

Abstract: An apparatus may include a drift tube assembly, arranged to transmit an ion beam. The drift tube assembly may include a first ground electrode; an RF drift tube assembly, disposed downstream of the first ground electrode; and a second ground electrode, disposed downstream of the RF drift tube assembly. The RF drift tube assembly may define a triple gap configuration. The apparatus may include a resonator, where the resonator comprises a toroidal coil, having a first end, connected to a first RF drift tube of the RF drift tube assembly, and a second end, connected to a second RF drift tube of the RF drift tube assembly.

Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

Abstract: Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.

Abstract: Apparatus and methods for measuring surface topography are described. The analysis apparatus and methods detect light reflected from the reflective backside of a cantilever assembly including a tip, calculate a background level (BGL) value obtained from an optical scan of a reference sample using a power spectral density (PSD) value obtained from a topographical scan of a reference sample to generate a correlational coefficient between the BGL and the PSD values. The correlational coefficient between the BGL and PSD values is used to measure the BGL value of additional EUV mask blanks by a topographical scan of the EUV mask blanks using the same tip mounted to the cantilever.

Abstract: A carrier head for chemical mechanical polishing includes a base, an actuator, a substrate mounting surface, and a retainer. The retainer includes an inner section and an outer section connected by a flexure. A bottom of the inner section of the retainer provides an inner portion of a lower surface configured to contact a polishing pad. An inner surface of the inner section extends upwardly from an inner edge of the lower surface to circumferentially surround the substrate mounting surface. The inner section of the retainer is positioned to receive a controllable load from the actuator and is vertically movable relative to the base. A bottom of the outer section of the retainer provides an outer portion of the lower surface. The outer section of the retainer is vertically fixed to the base. The inner section of the retainer is vertically movable relative to the outer section of the retainer.

Abstract: Embodiments include devices and methods for detecting material deposition and material removal performed by a wafer processing tool. In an embodiment, one or more micro sensors mounted on a process chamber of the wafer processing tool are capable of operating under vacuum conditions and/or may measure material deposition and removal rates in real-time during a plasma-less wafer fabrication process. Other embodiments are also described and claimed.

Abstract: Embodiments include systems and methods for determining a processing parameter of a processing operation. Embodiments include a diagnostic substrate for determining processing parameters of a processing operation. In an embodiment, the diagnostic substrate comprises a substrate, a circuit layer over the substrate, and a capping layer over the circuit layer. In an embodiment, a micro resonator sensor is in the circuit layer and the capping layer. In an embodiment, the micro resonator sensor comprises, a resonating body and one or more electrodes for inducing resonance in the resonating body.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in an organic light-emitting diode (OLED) display are described herein. The overhang structures are permanent to the sub-pixel circuit. The overhang structures include a conductive oxide. A first configuration of the overhang structures includes a base portion and a top portion with the top portion disposed on the base portion. In a first sub-configuration, the base portion includes the conductive oxide of at least one of a TCO material or a TMO material. In a second sub-configuration, the base portion includes a metal alloy material and the conductive oxide of a metal oxide surface. A second configuration of the overhang structures includes the base portion and the top portion with a body portion disposed between the base portion and the top portion. The body portion includes the metal alloy body and the metal oxide surface.

Abstract: There is provided a mask inspection system and a method of mask inspection. The method comprises: during a runtime scan of a mask of a semiconductor specimen, processing a plurality of aerial images of the mask acquired by the mask inspection system to calculate a statistic-based Edge Positioning Displacement (EPD) of a potential defect, wherein the statistic-based EPD is calculated using a Print Threshold (PT) characterizing the mask and is applied to each of the one or more acquired aerial images to calculate respective EPD of the potential defect therein; and filtering the potential defect as a “runtime true” defect when the calculated statistic-based EPD exceeds a predefined EPD threshold, and filtering out the potential defect as a “false” defect when the calculated statistic-based EPD is lower than the predefined EPD threshold. The method can further comprise after-runtime EPD-based filtering of the plurality of “runtime true” defects.

Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.

Abstract: Implementations described herein provide for thermal substrate processing apparatus including two thermal process chambers, each defining a process volume, and a substrate support disposed within each process volume. One or more remote plasma sources may be in fluid communication with the process volumes and the remote plasma sources may be configured to deliver a plasma to the process volumes. Various arrangements of remote plasma sources and chambers are described.

Abstract: Exemplary methods of forming a semiconductor structure may include forming a liner along sidewalls of a trench defined from a first surface of a semiconductor substrate. The liner may extend along the first surface of the semiconductor substrate. The methods may include filling the trench with a dielectric material. The methods may include removing the dielectric material and the liner from the first surface of the semiconductor substrate. The methods may include forming a layer of the liner across the first surface of the semiconductor substrate and the trench defined within the semiconductor substrate.

Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.

Abstract: Power supplies, waveform function generators and methods for controlling a plasma process are described. The power supplies or waveform function generators include a component for executing the method in which a waveform shape change index is determined during a plasma process and evaluated for compliance with a predetermined tolerance.

Abstract: Apparatus and methods for processing a substrate including an injector unit, comprising a leading reactive gas port extending along a length of the injector unit, a trailing reactive gas port extending along the length of the injector unit, and a merge vacuum port forming a boundary around and enclosing the leading reactive gas port and the trailing reactive gas port.