Abstract: A method and circuit for performing vector-matrix multiplication may include converting an input vector of binary-encoded values into analog signals using one-bit DACs, and sequentially performing a vector-matrix multiplication operation for each bit-order. The method may also include, for each sequentially performed operation, operating a switch that corresponds to a current bit-order. Operating the switch may cause a value corresponding to an output of the multiplier to be stored on a capacitor corresponding to the current bit-order. A time interval during which the switch is operated may be non-uniform with respect to time intervals for other switches, and the time interval may be based at least in part on a settling time of the capacitor. The method may also include performing a bit-order weighted summation of values stored on the plurality of capacitors to generate a result of the vector-matrix multiplication.

Abstract: A method for performing vector-matrix multiplication may include converting a digital input vector comprising a plurality of binary-encoded values into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs); sequentially performing, using an analog vector matrix multiplier and based on bit-order, vector-matrix multiplication operations using a weighting matrix for the plurality of analog signals to generate analog outputs of the analog vector matrix multiplier; sequentially performing an analog-to-digital (ADC) operation on the analog outputs of the analog vector matrix multiplier to generate binary partial output vectors; and combining the binary partial output vectors to generate a result of the vector-matrix multiplication.

Abstract: A radio-frequency (RF) power circuit for a multi-electrode cathode in a processing chamber may include an RF source and inductive element(s) that are conductively coupled to the RF source. A first inductive element may be inductively coupled to the inductive element(s), and the first inductive element may be configured to receive a first portion of RF power originating from the RF source and provide the first portion of the RF power for a first pedestal electrode. A second inductive element may also be inductively coupled to the inductive element(s), and the second inductive element may be configured to receive a second portion of RF power originating from the RF source through the inductive element(s) and provide the second portion of the RF power for a second pedestal electrode.

Abstract: An electrostatic clamping system including a platen, an electrostatic electrode associated with the platen, and a sealing cover having a concave lower surface defining a cavity and having a sealing ring extending about a periphery of the lower surface, the sealing cover movable relative to the platen for being moved onto, and being moved off of, a wafer disposed on the platen, the sealing cover further having an inlet valve for introducing a gas into a space between a cover body of the sealing cover and the wafer.

Abstract: A method of chemical mechanical polishing includes rotating a polishing pad about an axis of rotation, positioning a substrate against the polishing pad, the polishing pad having a groove that is concentric with the axis of rotation, oscillating the substrate laterally across the polishing pad such that a central portion of the substrate and an edge portion of the substrate are positioned over a polishing surface of the polishing pad for a first duration, and holding the substrate substantially laterally fixed in a position such that the central portion of the substrate is positioned over the polishing surface of the polishing pad and the edge portion of the substrate is positioned over the groove for a second duration.

Abstract: A method, a non-transitory computer readable medium and a detection system for determining locations of suspected defects of a substrate.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate; a multilayer stack of reflective layers on the substrate; a capping layer on the multilayer stack of reflecting layers; and an absorber layer on the capping layer, the absorber layer made from bismuth and iron.

Abstract: Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.

Abstract: Implementations described herein protect a substrate support from corrosive cleaning gases used at high temperatures. In one embodiment, a substrate support has a shaft having an outer wall. The substrate support has a heater. The heater has a body having a top surface, a side surface and a bottom surface extending from the outer wall of the shaft. The top surface is configured to support a substrate during plasma processing of the substrate. A covering is provided for at least two of the top surface, side surface and bottom surface. The covering is selected to resist corrosion of the body at temperatures in excess of about 400 degrees Celsius. A sleeve circumscribing the shaft, the sleeve and the outer wall of the shaft forming a space therebetween, the space adapted to flow a purge gas therethrough in a direction toward the body.

Abstract: An improved technique for determining height difference in patterns provided on semiconductor wafers uses real measurements (e.g., measurements from SEM images) and a height difference determination model. In one version of the model, a measurable variable of the model is expressed in terms of a function of a change in depth of shadow (i.e. relative brightness), wherein the depth of shadow depends on the height difference as well as width difference between two features on a semiconductor wafer. In another version of the model, the measurable variable is expressed in terms of a function of a change of a measured distance between two characteristic points on the real image of a periodic structure with respect to a change in a tilt angle of a scanning electron beam.

Abstract: A method of coating particles includes dispensing particles into a vacuum chamber to form a particle bed in at least a lower portion of the chamber that forms a half-cylinder, evacuating the chamber through a vacuum port in an upper portion of the chamber, rotating a paddle assembly such that a plurality of paddles orbit a drive shaft to stir the particles in the particle bed, injecting a reactant or precursor gas through a plurality of channels into the lower portion of the chamber as the paddle assembly rotates to coat the particles, and injecting the reactant or precursor gas or a purge gas through the plurality of channels at a sufficiently high velocity such that the reactant or precursor a purge gas de-agglomerates particles in the particle bed.

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

Abstract: Extreme ultraviolet (EUV) mask blanks, methods for their manufacture and production systems therefor are disclosed. The EUV mask blanks comprise a substrate, a multilayer stack of reflective layers on the substrate, a capping layer on the multilayer stack of reflecting layers, and an absorber on the capping layer. The absorber comprising a plurality of bilayers comprising a first layer of silicon and a second layer selected from the group consisting of TaSb, CSb, TaNi, TaCu, SbN, CrN, Cr, Ir, Pd, Re, Os, Cd, Co, Ag, Pt, oxides of TaSb, CSb, TaNi, TaCu, SbN, CrN, Cr, Ir, Pd, Re, Os, Cd, Co, Ag, Pt, and nitrides of TaSb, CSb, TaNi, TaCu, Cr, Ir, Pd, Re, Os, Cd, Co, Ag, and Pt.

Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

Abstract: Exemplary semiconductor processing chambers may include a faceplate assembly characterized by at least one surface defining a number of voids. Each void is configured to receive an interchangeable thermal body that can be selected from multiple interchangeable thermal bodies. Exemplary semiconductor processing chambers may also include a gas box characterized by movable members. Each movable member is configured to engage a delivery port and is movable to provide flow control for a gas being delivered to the processing volume through a gas flow path. Zoned flow and/or temperature control may be provided by the faceplate assembly, the gas box, or both.

Abstract: A deposition system, and a method of operation thereof are disclosed. The deposition system comprises a cathode assembly comprising a rotating magnet assembly including a plurality of outer peripheral magnets surrounding an inner peripheral magnet.

Abstract: A selector device may include a first electrode, a tunneling layer, and a ferroelectric layer. The tunneling layer may be between the first electrode and the ferroelectric layer, and a thickness and dielectric constant of the tunneling layer relative to a thickness and dielectric constant of the ferroelectric layer may cause a depolarizing electric field induced in the first tunneling layer to be greater than or approximately equal to an electric field induced in an opposite direction by ferroelectric dipoles in the ferroelectric layer when a voltage is applied across the selector device. The device may also include a second electrode, and the ferroelectric layer may be between the tunneling layer and the second electrode. A second ing layer may also be added between the ferroelectric layer and the second electrode for bipolar selectors.

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

Abstract: Exemplary semiconductor processing systems may include a processing chamber, an inductively coupled plasma (ICP) source disposed in or on the processing chamber, and a support configured to position a substrate. The support can be disposed at least partially within the processing chamber and can include a bias electrode. An ion screen may be disposed within the chamber to be above a substrate on the support. The ion screen is semitransparent to ions and electrons so that the density of plasma sustained above the ion screen is unaffected by RF bias power applied to the bias electrode. Plasma energy control is therefore accomplished while maintaining independence of plasma density from RF bias power so that high ion energy and low bias current may be afforded.

Abstract: Exemplary semiconductor processing systems may include a chamber body comprising sidewalls and a base. The systems may include a substrate support extending through the base of the chamber body. The substrate support may include a support plate defining a plurality of channels through an interior of the support plate. Each channel of the plurality of channels may include a radial portion extending outward from a central channel through the support plate. Each channel may also include a vertical portion formed at an exterior region of the support plate fluidly coupling the radial portion with a support surface of the support plate. The substrate support may include a shaft coupled with the support plate. The central channel may extend through the shaft. The systems may include a fluid source coupled with the central channel of the substrate support.