Abstract: A server includes a processor to supply a torque command to an amplifier that controls a motor that drives a linkage; include, in the torque command, an alternating signal wave that is to test a frequency response of the motor and the linkage; receive, from the amplifier, an instantaneous torque value of the motor and an instantaneous mechanical parameter value of the linkage at each time step according to a sampling rate and over a period of time; store an aggregate of both these values; determine, for a first frequency of the alternating signal wave, a magnitude and phase shift between the aggregate of the instantaneous mechanical parameter values and the aggregate of the instantaneous torque values; and generate, using an aggregate of magnitude and phase shift data for multiple frequencies of the alternating signal wave, a fingerprint to be used in performing diagnostics of motor and linkage.

Abstract: A method may include providing a substrate on a clamp, and directing radiation from an illumination source to the substrate when the substrate is disposed on the clamp during substrate processing, wherein the radiation is characterized by a radiation energy, wherein at least a portion of the radiation energy is equal to or greater than 2.5 eV.

Abstract: Embodiments of the present invention provide a plasma chamber design that allows extremely symmetrical electrical, thermal, and gas flow conductance through the chamber. By providing such symmetry, plasma formed within the chamber naturally has improved uniformity across the surface of a substrate disposed in a processing region of the chamber. Further, other chamber additions, such as providing the ability to manipulate the gap between upper and lower electrodes as well as between a gas inlet and a substrate being processed, allows better control of plasma processing and uniformity as compared to conventional systems.

Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

Abstract: A method of determining whether a substrate is properly polished includes obtaining an image of the substrate, obtaining intensity values of a luminance plane for the image, generating an intensity histogram from the intensity values of the luminance plane, and analyzing the intensity histogram to determine whether the intensity histogram meets one or more criteria.

Abstract: A method of preparing a pharmaceutical composition having a drug-containing core enclosed by one or more metal oxide materials is provided. The method includes the sequential steps of (a) loading the particles comprising the drug into a reactor, (b) applying a vaporous or gaseous metal precursor to the particles in the reactor, (c) performing one or more pump-purge cycles of the reactor using inert gas, (d) applying a vaporous or gaseous oxidant to the particles in the reactor, and (e) performing one or more pump-purge cycles of the reactor using inert gas. The temperature of the particles does not exceed 35° C. This produces a pharmaceutical composition comprising a drug containing core enclosed by one or more metal oxide materials.

Abstract: Embodiments of the present disclosure include positioning a mask over a substrate, wherein the mask has a planar surface separated from a top surface of the substrate by a mask distance, and wherein a mask opening is provided through the planar surface. The method may further include positioning a mask element across the mask opening, the mask element including one or more solid portions and one or more openings, and depositing, through the mask opening, a deposition material onto the substrate, wherein the deposition material has a variable profile as a result of the one or more solid portions and the one or more openings.

Abstract: Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component). In some embodiments, a method may include providing a plurality of device structures extending from a base, each of the plurality of device structures including a first sidewall opposite a second sidewall and a top surface extending between the first and second sidewalls, and providing a seed layer over the plurality of device structures. The method may further include forming a dielectric layer along just the top surface and along an upper portion of the first and second sidewalls using an angled deposition delivered to the plurality of device structures at a non-zero angle of inclination relative to a perpendicular extending from an upper surface of the base, and forming a fill material within one or more trenches defined by the plurality of device structures.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise an oxide layer and a semiconductor material layer between source regions and drain regions of the device. The method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer. An alternative method includes growing a conformal epitaxial layer on a nanosheet channel layer, followed by a surface treatment, and then radical plasma oxidation (RPO) to oxidize the conformal epitaxial layer.

Abstract: Exemplary substrate processing systems may include a body that defines processing and transfer regions. The systems may include a liner atop the body. The systems may include a faceplate atop the liner. The systems may include a support within the body. The support may be vertically translatable between process and transfer positions. The support may include a plate having a heater. The support may include a shaft coupled with the plate. The support may include a bowl about the shaft below the plate. The bowl may be in alignment with the liner. The support may include springs that push the bowl upward as the support translates to the process position. The support may include straps that couple the plate and bowl. The support may include a hard stop. The bowl may contact the liner in the process position and may be spaced apart from the liner in the transfer position.

Abstract: Exemplary semiconductor processing systems include a processing chamber, a power supply, and a chuck disposed at least partially within the processing chamber. The chuck includes a chuck body defining a vacuum port. The chuck also includes first and second coplanar electrodes embedded in the chuck body and connected to the power supply. In some examples, coplanar electrodes include concentric electrodes defining a concentric gap in between. Exemplary semiconductor processing methods may include activating the power supply for the electrostatic chuck to secure a semiconductor substrate on the body of the chuck and/or activating the vacuum port defined by the body of the electrostatic chuck. Some processing can be carried out at increased pressure, while other processing can be carried out at reduced pressure with increased chucking voltage.

Abstract: Semiconductor processing systems according to embodiments of the present technology may include a chamber body having sidewalls and a base. The chamber body may define an internal volume. The systems may include a substrate support assembly having a shaft and a platen coupled with the shaft along a first surface of the platen. The semiconductor processing systems may include a cover plate positioned on the platen of the substrate support assembly along a second surface of the platen opposite the first surface. The cover plate may include a flange extending about an exterior region of the cover plate. The flange may be in direct contact with the platen. The cover plate may include an upper wall vertically offset from the flange. An interior volume may be defined between the upper wall and the platen of the substrate support assembly.

Abstract: Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.

Abstract: Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

Abstract: Exemplary semiconductor processing systems may include a remote plasma source and a processing chamber. The processing chamber may include a gasbox defining an access into the processing chamber. The systems may include an adapter positioned between the remote plasma source and the processing chamber. The adapter may include a mounting block defining a central aperture. The remote plasma source may be seated on a first surface of the mounting block. The adapter may include a mounting plate characterized by a first surface on which the mounting block is seated. The mounting plate may define a central aperture axially aligned with the central aperture defined through the mounting block. The mounting plate may define a recess in the first surface of the mounting plate extending about the central aperture through the mounting plate. The recess may form a volume between the mounting block and the mounting plate.

Abstract: A semiconductor processing system includes a remote plasma source (RPS), a faceplate, and an output manifold positioned between the RPS and the faceplate. The output manifold is characterized by a plurality of purge outlets that are fluidly coupled with a purge gas source and a plurality of deposition outlets that are fluidly coupled with a deposition gas source. A delivery tube extends between and fluidly couples the RPS and the faceplate. The delivery tube is characterized by a generally cylindrical sidewall that defines an upper plurality of apertures that are arranged in a radial pattern. Each of the upper apertures is fluidly coupled with one of the purge outlets. The generally cylindrical sidewall defines a lower plurality of apertures that are arranged in a radial pattern and below the upper plurality of apertures. Each of the lower apertures is fluidly coupled with one of the deposition outlets.

Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.

Abstract: Embodiments of the disclosure include methods and apparatus for electrostatically coupling a mask to a substrate support in a deposition chamber. In one embodiment, a substrate support is disclosed that includes a substrate receiving surface, a recessed portion disposed about a periphery of the substrate receiving surface, an electrostatic chuck disposed below the substrate receiving surface, and a plurality of compressible buttons disposed within a respective opening formed in the recessed portion that form an electrical circuit with the electrostatic chuck.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The assemblies may include a support stem coupled with the electrostatic chuck body. The assemblies may include a heater embedded within the electrostatic chuck body. The assemblies may include an electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The assemblies may include a power transmission rod coupled with the electrode. The power transmission rod may include a material characterized by a coefficient of thermal expansion of less than or about 10×10?6/° C.

Abstract: Exemplary substrate support assemblies include an electrostatic chuck body defining a substrate platform. The substrate platform may be characterized by an upper surface. The platform may define a purge aperture. The platform may include a plurality of mesas that are disposed in an inner region of the upper surface. Each of the mesas may protrude upward from the upper surface. The platform may include a sealing band that extends upward from the upper surface in a circumferential pattern and partially encircles the inner region of the upper surface. Top surfaces of the mesas and sealing band may form a support surface for a substrate. The sealing band may define a number of gaps. The assemblies may include a support stem coupled with the electrostatic chuck body, a heater embedded within the electrostatic chuck body, and a backside gas source that is coupled with the purge aperture of the support surface.