Abstract: Apparatus and methods for spatial atomic layer deposition including at least one first exhaust system and at least one second exhaust system. Each exhaust system including a throttle valve and a pressure gauge to control the pressure in the processing region associated with the individual exhaust system.

Abstract: Electroplating systems according to embodiments of the present technology may include a plating chamber configured to deposit metal material onto substrates positioned in the plating chamber. The plating chamber may include a rotor and a vessel. The electroplating systems may include at least one of baffle positioned in the plating chamber. The at least one baffle may define a plurality of slots. The at least one baffle may be configured to limit or prevent fluid from splashing the rotor or the plating chamber during operation of the plating chamber.

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate.

Abstract: Gas distribution assemblies and methods for providing a flow of gases to a process station are described. The gas distribution assemblies comprise a pumping liner with a showerhead and a gas funnel positioned therein. The pumping liner has an inner wall that slants at a first angle relative to a central axis of the gas distribution assembly so that the inner wall adjacent the bottom wall of the pumping liner is closer to the central axis than the inner wall adjacent the top wall. The gas funnel and pumping liner form a plenum between the outer wall of the gas funnel, a cavity in the bottom wall of the gas funnel and the inner wall of the pumping liner.

Abstract: A method reduces differences in chucking forces that are applied by two electrodes of an electrostatic chuck, to a substrate disposed atop the chuck. The method includes providing initial chucking voltages to each of the two electrodes, and measuring an initial current provided to at least a first electrode of the two electrodes. The method further includes initiating a process that affects a DC voltage of the substrate, then measuring a modified current provided to at least the first electrode, and determining, based at least on the initial current and the modified current, a modified chucking voltage for a selected one of the two electrodes, that will reduce chucking force imbalance across the substrate. The method also includes providing the modified chucking voltage to the selected one of the two electrodes.

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor through a faceplate into the processing region of the semiconductor processing chamber. The faceplate may have an impedance of at least 5.75 deciohm. The methods may include depositing a silicon-containing material on the semiconductor substrate.

Abstract: Embodiments of the disclosure relate to methods and materials for forming barrier layers with enhanced barrier performance and/or reduced via resistance. Some embodiments of the disclosure provide methods for passivating a metal surface by exposing the metal surface to a metal complex comprising an organic ligand with at least three carbon atoms and a double or triple bond that eta bonds with a central metal atom. Some embodiments provide barrier layers within vias which enable a reduction in resistance of at least 25% as a result of thinner barrier layers with equivalent barrier properties.

Abstract: Exemplary substrate processing system may include a chamber body that defines a processing region. The systems may include a liner positioned atop the chamber body. The liner may include first disconnect members. The systems may include a faceplate that is positioned atop the liner. The systems may include a support disposed within the chamber body. The support may include a plate comprising a heater. The plate may include second disconnect members. The support may include a shaft coupled with the plate. The support may include a dynamic plate disposed about the shaft below the plate. The support may include metallic straps that couple the plate with the dynamic plate. The dynamic plate may include inner disconnect members and outer disconnect members. Inner disconnect members may be engageable with second disconnect members in a transfer position. Outer disconnect members may be engageable with first disconnect members in a process position.

Abstract: Exemplary processing methods may include forming a plasma of a cleaning precursor in a remote region of a semiconductor processing chamber. The methods may include flowing plasma effluents of the cleaning precursor into a processing region of the semiconductor processing chamber. The methods may include contacting a substrate support with the plasma effluents for a first period of time. The methods may include lowering the substrate support from a first position to a second position while continuing to flow plasma effluents of the cleaning precursor. The methods may include cleaning the processing region of the semiconductor processing chamber for a second period of time.

Abstract: Exemplary support assemblies may include an electrostatic chuck body defining a substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include a heater embedded within the electrostatic chuck body. The substrate support assemblies may include a first bipolar electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The first bipolar electrode may include at least two separated mesh sections, with each mesh section characterized by a circular sector shape. The substrate support assemblies may include a second bipolar electrode embedded within the electrostatic chuck body between the heater and the substrate support surface. The second bipolar electrode may include a continuous mesh extending through the at least two separated mesh sections of the first bipolar electrode.

Abstract: Semiconductor processing systems and method are described that may include flowing deposition precursors into a substrate processing region of a semiconductor processing chamber, where the substrate processing region includes an electrostatic chuck. The methods may further include depositing a seasoning layer on the electrostatic chuck from the deposition precursors to form a seasoned electrostatic chuck. The seasoning layer may be characterized by a dielectric constant greater than or about 3.5. The methods may still further include applying a voltage to the seasoned electrostatic chuck of greater than or about 500 V. The seasoned electrostatic chuck may be characterized by a leakage current of less than or about 25 mA when the voltage is applied.

Abstract: There is provided a system and method of automatic optimization of an examination recipe. The method includes obtaining one or more inspection images each representative of at least a portion of the semiconductor specimen, the one or more inspection images being indicative of respective defect candidates selected from a defect map using a first classifier included in the examination recipe; obtaining label data respectively associated with the one or more inspection images and informative of types of the respective defect candidates; extracting inspection features characterizing the one or more inspection images; retraining the first classifier using the first features and the label data, giving rise to a second classifier; and optimizing the examination recipe by replacing the first classifier with the second classifier; wherein the optimized examination recipe is usable for examining a subsequent semiconductor specimen.

Abstract: A collimator that is biasable is provided. The ability to bias the collimator allows control of the electric field through which the sputter species pass. In some implementations of the present disclosure, a collimator that has a high effective aspect ratio while maintaining a low aspect ratio along the periphery of the collimator of the hexagonal array of the collimator is provided. In some implementations, a collimator with a steep entry edge in the hexagonal array is provided. It has been found that use of a steep entry edge in the collimator reduces deposition overhang and clogging of the cells of the hexagonal array. These various features lead to improve film uniformity and extend the life of the collimator and process kit.

Abstract: The present disclosure generally relates to an isolation device for use in processing systems. The isolation device has a body with an inlet opening disposed at a first end coupled to a processing system component such as a remote plasma source and outlet openings, for example two, disposed at a second end which are coupled to a processing system component such as a process chamber. Flaps disposed within the body are actuatable to an open position from a closed position or to a closed position from an open position, to selectively allow or prevent passage of a fluid from the processing system component coupled to the isolation device to the other processing system component coupled thereto.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: A method of method of operating a multibeamlet charged particle device is disclosed. In the method, a target attached to a stage is translated, and each step of selecting beamlets, initializing beamlets, and exposing the target is repeated. The step of selecting beamlets includes passing a reconfigurable plurality of selected beamlets through the blanking circuit. The step of initializing beamlets includes pointing each of the selected beamlets in an initial direction. The step of exposing the target includes scanning each of the selected beamlets from the initial direction to a final direction, and irradiating a plurality of regions of the target on the stage with the selected beamlets.

Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Embodiments of the present technology may include semiconductor processing methods that include depositing a film of semiconductor material on a substrate in a substrate processing chamber. The deposited film may be sampled for defects at greater than or about two non-contiguous regions of the substrate with scanning electron microscopy. The defects that are detected and characterized may include those of a size less than or about 10 nm. The methods may further include calculating a total number of defects in the deposited film based on the sampling for defects in the greater than or about two non-contiguous regions of the substrate. At least one deposition parameter may be adjusted as a result of the calculation. The adjustment to the at least one deposition parameter may reduce the total number of defects in a deposition of the film of semiconductor material.

Abstract: A method and circuit for performing multi-layer vector-matrix multiplication operations may include, at a first multiplier-accumulator (MAC) layer, converting a digital input vector using one-bit digital to analog converters (DACs); sequentially performing vector-matrix multiplication operations for the analog DAC signals; and sequentially performing an analog-to-digital (ADC) operation on outputs of the vector-matrix multiplication operations to generate binary partial output vectors. At a second MAC layer, the method and circuit may sequentially receive the binary partial output vectors from the first MAC layer at multi-bit DACs; and sequentially perform vector-matrix multiplication operations to generate a summed binary output for the second MAC layer.