Abstract: Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. Some embodiments of the methods include conventional dipole engineering techniques such as dipole first processes and/or dipole last processes without the need for repairing the interfacial layer after treatment (in dipole first processes) or repairing the high-K dielectric layer after the annealing process (in dipole last processes).

Abstract: An electron beam spot shape reconstruction unit that includes a processing circuit and a memory unit. The processing circuit is configured to reconstruct a shape of an electron beam spot by (i) obtaining multiple groups of images of circular targets of a sample, wherein different groups of images of the multiple groups of images are associated with different polar angles; (ii) processing at least two of the multiple groups of images to determine first-axis edge width information and second-axis edge width information; and (iii) reconstructing the electron beam spot shape based on the first-axis edge width information and second-axis edge width information.

Abstract: Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-containing precursor and a metal-containing precursor. The silicon-containing precursor and the metal-containing precursor may be fluidly isolated prior to reaching the processing region. A substrate may be housed within the processing region. The methods may include generating plasma effluents of the deposition precursors. The methods may include forming a layer of silicon-and-metal-containing material on the substrate.

Abstract: Multiple electron beam optics that includes a detection unit that comprises an array of sensors, and a cross talk reduction unit. For each sensor of multiple sensors of the array of sensors: (i) the sensor includes an aperture and a sensing region that is configured to sense relevant backscattered electrons, the relevant backscattered electrons are emitted from the sample as a result of an illumination of the sample with a primary electron beam that is associated with the sensor and passed through the aperture; and (ii) the crosstalk reduction unit is configured to at least partially prevent a detection, by the sensor, of cross talk backscattered electrons, the cross talk backscattered electrons are emitted from the sample as result of an illumination of the sample by one or more primary beams not associated with the sensor.

Abstract: Exemplary semiconductor processing methods may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-carbon-and-hydrogen-containing precursor. A substrate may be disposed within the processing region. The methods may include forming plasma effluents of the deposition precursors, wherein the plasma effluents are formed at a plasma power of less than or about 2,000 W. The methods may include depositing a layer of silicon-containing material on the substrate.

Abstract: Exemplary methods of semiconductor processing may include providing deposition precursors to a processing region of a semiconductor processing chamber. The deposition precursors may include a silicon-and-halogen-containing precursor and a metal-containing precursor. A substrate may be housed within the processing region. The methods may include generating plasma effluents of the deposition precursors. The methods may include forming a layer of silicon-and-metal-containing material on the substrate.

Abstract: Exemplary diffusers for a substrate processing chamber may include a diffuser body that is characterized by a first surface on an inlet side of the diffuser body and a second surface on an outlet side of the diffuser body. The diffuser body may define a plurality of apertures through a thickness of the diffuser body. The first surface may not be anodized. The second surface may be anodized.

Abstract: Provided are methods of forming vias with decreased resistance by selectively depositing a barrier layer on an insulating layer and not on a metallic surface. Some embodiments of the disclosure utilize a planar hydrocarbon to form a blocking layer on metallic surfaces. Deposition is performed to selectively deposit on the unblocked insulating surfaces.

Abstract: Embodiments provided herein generally include apparatus, e.g., plasma processing systems and methods for the plasma processing of a substrate in a processing chamber. In some embodiments, aspects of the apparatus and methods are directed to improving process uniformity across the surface of the substrate, reducing defectivity on the surface of the substrate, or both. In some embodiments, the apparatus and methods provide for improved control over the uniformity of a plasma formed over the edge of a substrate and/or the distribution of ion energies at the surface of the substrate. The improved control over the plasma uniformity may be used in combination with substrate handling methods, e.g., de-chucking methods, to reduce particulate-related defectivity on the surface of the substrate. In some embodiments, the improved control over the plasma uniformity is used to preferentially clean accumulated processing byproducts from portions of the edge ring during an in-situ plasma chamber cleaning process.

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Abstract: An apparatus includes a substrate holder, a first actuator to rotate the substrate holder, a second actuator to move the substrate holder linearly, a first sensor to generate one or more first measurements or images of the substrate, a second sensor to generate one or more second measurements of target positions on the substrate, and a processing device. The processing device estimates a position of the substrate on the substrate holder and causes the first actuator to rotate the substrate holder about a first axis. The rotation causes an offset between a field of view of the second sensor and a target position on the substrate due to the substrate not being centered on the substrate holder. The processing device causes the second actuator to move the substrate holder linearly along a second axis to correct the offset. The processing device determines a profile across a surface of the substrate based on the one or more second measurements of the target positions.

Abstract: A reactor for coating particles includes a vacuum chamber configured to hold particles to be coated, a vacuum port to exhaust gas from the vacuum chamber via the outlet of the vacuum chamber, a chemical delivery system configured to flow a process gas into the particles via a gas inlet on the vacuum chamber, one or more vibrational actuators located on a first mounting surface of the vacuum chamber, and a controller configured to cause the one or more vibrational actuators to generate a vibrational motion in the vacuum chamber sufficient to induce a vibrational motion in the particles held within the vacuum chamber.

Abstract: Apparatus and methods for gas distribution assemblies are provided. In one aspect, a gas distribution assembly is provided comprising an annular body comprising an annular ring having an inner annular wall, an outer wall, an upper surface, and a bottom surface, an upper recess formed into the upper surface, and a seat formed into the inner annular wall, an upper plate positioned in the upper recess, comprising a disk-shaped body having a plurality of first apertures formed therethrough, and a bottom plate positioned on the seat, comprising a disk-shaped body having a plurality of second apertures formed therethrough which align with the first apertures, and a plurality of third apertures formed between the second apertures and through the bottom plate, the bottom plate sealingly coupled to the upper plate to fluidly isolate the plurality of first and second apertures from the plurality of third apertures.

Abstract: A metrology system for obtaining a measurement representative of a thickness of a layer on a substrate includes a camera positioned to capture a color image of at least a portion of the substrate. A controller is configured to receive the color image from the camera, store a predetermined path in a coordinate space of at least two dimension including a first color channel and a second color channel, store a function that provides a value representative of a thickness as a function of a position on the predetermined path, determine a coordinate of a pixel in the coordinate space from color data in the color image for the pixel, determine a position of a point on the predetermined path that is closest to the coordinate of the pixel, and calculate a value representative of a thickness from the function and the position of the point on the predetermined path.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: A method includes receiving first sensor data, generated during a manufacturing process by sensors associated with a substrate manufacturing chamber. The method further includes receiving simulated sensor data generated by a trained physics-based model. The method further includes determining which one or more components of the manufacturing chamber contribute to a difference between the first sensor data and the simulated sensor data. The method further includes causing performance of a corrective action in view of the difference.

Abstract: A lamp and epitaxial processing apparatus are described herein. In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.

Abstract: Apparatus and methods for calibrating a height-adjustable edge ring are described herein. In one example, a calibration jig for positioning an edge ring relative to a reference surface is provided that includes a transparent plate, a plurality of sensors coupled to a first side of the transparent plate, and a plurality of contact pads coupled to an opposing second side of the transparent plate.

Abstract: The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.