Abstract: A plasma doping system including a plasma doping chamber, a platen mounted in the plasma doping chamber for supporting a workpiece, a source of ionizable gas coupled to the chamber, the ionizable gas containing a desired dopant for implantation into the workpiece, a plasma source for producing a plasma having a plasma sheath in a vicinity of the workpiece, the plasma containing positive ions of the ionizable gas, and accelerating said positive ions across the plasma sheath toward the platen for implantation into the workpiece, a shield ring surrounding the platen and adapted to extend the plasma sheath beyond an edge of the workpiece, and a cover ring disposed on top of the shield ring and adapted to mitigate sputtering of the shield ring, wherein the cover ring comprises a crystalline base layer and a non-crystalline top layer.

Abstract: Electrostatic chucks and method for forming the same are described herein. The electrostatic chucks include a backside gas passage having a ceramic porous plug secured therein by a ceramic body of the chuck with a ceramic-to-ceramic body. In one example, ceramic porous plug is sintered with the ceramic body.

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. The thermal process chamber includes a substrate support, a first plurality of heating elements disposed over or below the substrate support, and a spot heating module disposed over the substrate support. The spot heating module is utilized to provide local heating of cold regions on a substrate disposed on the substrate support during processing. Localized heating of the substrate improves temperature profile, which in turn improves deposition uniformity.

Abstract: Embodiments of the present disclosure generally relate to apparatus for substrate processing, and more specifically to apparatus for rotating substrates and to uses thereof. In an embodiment, an apparatus for rotating a substrate is provided. The apparatus includes a levitatable rotor comprising a plurality of magnets embedded therein, a plurality of gas bearings positioned to levitate the levitatable rotor, and a stator magnetically coupled to the levitatable rotor, the stator for producing a rotating magnetic field. Apparatus for processing a substrate with the apparatus for rotating substrates as well as methods of use are also described.

Abstract: Disclosed herein is a plasma-resistant chamber component and a method for manufacturing the same. A plasma-resistant chamber component of a semiconductor processing chamber that generates a plasma environment includes a ceramic article having multiple polished apertures. A roughness of the multiple polished apertures is less than 32 ?in.

Abstract: Embodiments disclosed herein include a method for field adjusting calibrating factors of a plurality of RF impedance matches for control of a plurality of plasma chambers. In an embodiment, the method comprises collecting and storing in a memory data from operation of the plurality of RF impedance matches, and finding a tune space for each of the plurality of RF impedance matches from the collected data. In an embodiment, the method further comprises finding adjustments to account for variability in each of the plurality of RF impedance matches, finding adjustments to variable tuning elements of the plurality of RF impedance matches to account for time varying and process related load impedances, and the method further comprises obtaining operating windows for the variable tuning elements in the plurality of RF impedance matches.

Abstract: An apparatus and method for etching a material layer with a cyclic etching and deposition process. The method for etching a material layer on a substrate includes: (a) etching at least a portion of a material layer (302) on a substrate (101) in an etch chamber (100) to form an open feature (360) having a bottom surface (312) and sidewalls in the material layer (302); (b) forming a protection layer (314) on the sidewalls and the bottom surface (312) of the open feature (360) from a protection layer (314) gas mixture comprising at least one carbon-fluorine containing gas; (c) selectively removing the protection layer (314) formed on the bottom surface (312) of the open feature (360) from a bottom surface (312) open gas mixture comprising the carbon-fluorine containing gas; and (d) continuingly etching the material layer (302) from the bottom surface (312) of the open feature (360) until a desired depth of the open feature (360) is reached.

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

Abstract: Vapor deposition precursor recovery systems and methods are provided. Methods and systems include a precursor container housing a precursor material and a carrier gas container housing a carrier gas. Systems and methods include a condenser assembly having a condenser in fluid connection with an exhaust line, a recycled precursor container, and a cooling circuit. Systems and methods include a vaporizer having one or more inlets in fluid connection with the precursor container and the carrier gas container, and an outlet in fluid connection with a gas distributor and the condenser assembly. Systems and methods include where the condenser is maintained at an internal temperature of greater than or about 10° C. below a boiling point of the precursor material and greater than or about 10° C. above a boiling point of the carrier gas.

Abstract: Approaches herein provide devices and methods for forming gate-all-around transistors with improved NBTI. One method may include forming a gate-all-around (GAA) stack including a plurality of alternating first layers and second layers, and forming a source/drain (S/D) cavity through the plurality of alternating first layers and second layers. The method may further include forming an inner spacer in the S/D cavity, adjacent the plurality of alternating first layers and second layers, performing a first implant by directing fluorine ions to the GAA stack, through the S/D cavity, and forming a S/D material in the S/D cavity following the first implant.

Abstract: Embodiments of the disclosure relate to methods of depositing seam-free gapfill. In some embodiments, the gapfill consists of titanium nitride. The gapfill methods comprise forming a first layer and a second layer. The firs layer is formed without treatment or densification, while the second layer is formed with periodic treatment. The resulting gapfill in advantageously seam-free.

Abstract: A chiplet-based architecture may quantize, or reduce, the number of bits at various stages of the data path in an artificial-intelligence processor. This architecture may leverage the synergy between quantizing multiple dimensions together to greatly decrease the memory usage and data path bandwidth. Internal weights may be quantized statically after a training procedure. Accumulator bits and activation bits may be quantized dynamically during an inference operation. New hardware logic may be configured to quantize the outputs of each operation directly from the core or other processing node before the tensor is stored in memory. Quantization may use a statistic from a previous tensor for a current output tensor, while also calculating a statistic to be used on a subsequent output tensor. In addition to quantizing based on a statistic, bits can be further quantized using a Kth percentile clamping operation.

Abstract: Embodiments of the disclosure include an apparatus and method of cleaning a substrate. The disclosure describes a method of cleaning a substrate includes supplying a gas at a gas temperature and a gas mass flow rate to a nozzle. The method also includes supplying a liquid at a liquid temperature and a liquid mass flow rate to the nozzle. The method also includes mixing the gas with the liquid in the nozzle to form a fluid mixture having a mixture temperature of not more than about 10° C. below the liquid temperature. The method also includes spraying the fluid mixture onto a surface of the substrate through an orifice in the nozzle.

Abstract: Disclosed herein are approaches for creating high electron mobility transistors with reduced contact resistance. In one approach, a method of forming a semiconductor device may include applying a first patterned mask on top of layered stack, wherein the layered stack includes a substrate, a buffer layer disposed over the substrate, a channel layer disposed above the buffer layer, and a barrier layer disposed above the channel layer. The method may further include forming, through an opening of the patterned mask, a source/drain contact in the barrier layer by delivering a first implant to the layered stack, and performing an etch process to form a contact opening in the source/drain contact. The method may further include performing a second implant to the source/drain contact, wherein the second implant is directed into the contact opening.

Abstract: Disclosed herein is a system for non-destructive tomography of specimens. The system includes a scanning electron microscope (SEM) and a processor(s). The SEM is configured to obtain a sinogram of a tested specimen, parameterized by a vector {right arrow over (s)}, by projecting e-beams on the tested specimen, at each of a plurality of projection directions and offsets, and. for each e-beam, measuring a respective intensity of electrons returned from the tested specimen, The processor(s) is configured to obtain a tomographic map, pertaining to the tested specimen, by determining values indicative of components of a vector {right arrow over (t)} defined by an equation W{right arrow over (t)}={right arrow over (s)}. W is a matrix with components wij specifying a contribution of a j-th voxel in a nominal specimen to an i-th element of a nominal sinogram of the nominal specimen. The matrix W accounts for e-beam expansion and attenuation with depth within the nominal specimen.

Abstract: Methods of semiconductor processing may include providing a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed on a substrate support within the processing region. A layer of silicon-and-nitrogen-containing material may be disposed on the substrate. The methods may include forming plasma effluents of the hydrogen-containing precursor. The methods may include contacting the layer of silicon-and-nitrogen-containing material with plasma effluents of the hydrogen-containing precursor. The contacting may etch a portion of the layer of silicon-and-nitrogen-containing material.

Abstract: Disclosed are approaches for to fabricating memory device channel holes using a doped film layer. One approach may include providing a substrate and forming a vertical stack over the substrate, wherein the vertical stack includes a plurality of alternating material layers. The method may further include forming a channel hole through the vertical stack, forming an oxide-nitride-oxide layer along a sidewall of the channel hole, forming a silicon layer over the oxide-nitride-oxide layer, forming an etch stop layer over the silicon layer, forming a fluorine-doped silicon layer over the etch step layer, and annealing the vertical stack.

Abstract: Methods of semiconductor processing may include forming a plasma of a carbon-containing material within a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a backside of a substrate housed within the processing region of the semiconductor processing chamber. A front side of the substrate may be maintained substantially free of carbon-containing material. The methods may include performing an etch process on the front-side of the substrate. The methods may include removing the carbon-containing material from the backside of the substrate.

Abstract: A system can provide in-situ analysis of at least some of a plurality of targets simultaneously during a fabrication process. The system can include a semiconductor processing tool having a chamber. The system can also include a sample arranged within the chamber, the sample having the plurality of targets with different feature orientations and/or feature geometries. The semiconductor processing tool can be configured to perform the fabrication process on the sample. Additionally, the system can include a metrology tool integrated with the semiconductor processing tool. The metrology tool can provide the in-situ analysis of at least some of the plurality of targets simultaneously during the fabrication process.

Abstract: A method includes determining, by a processing device, whether a first process recipe including a set of Pareto efficient parameters is to be selected from a set of process recipes, wherein the set of Pareto efficient parameters fail to satisfy each target property of a set of target properties for processing the component, in response to determining that a first process recipe is not to be selected from a set of process recipes for processing the component, selecting, by the processing device from the set of process recipes, a second process recipe including a set of parameters satisfying each target property of the set of target properties, and causing, by the processing device, the component to be processed by a process tool using the second process recipe.