Abstract: A substrate holding apparatus for use in ion implanters includes two or more substrate holders that can adopt interchangeable positions, thereby allowing one substrate holder to scan a substrate through an ion beam while substrates can be swapped on the other substrate holder. The substrate holder assembly includes a base rotatable about a first axis and at least two support arms extending from the base to ends provided with substrate holders. Rotating the base allows the substrate holders to move between designated positions. One designated position may correspond to a position for implanting a substrate and another designated position may correspond to a loading/unloading station.
Abstract: Embodiments of the invention are directed to methods and apparatus for processing of a solar substrate for making a photovoltaic device. In particular, methods and apparatus for creating a negatively charged passivation layer by are provided.
Type:
Application
Filed:
February 6, 2009
Publication date:
August 12, 2010
Applicant:
Applied Materials, Inc.
Inventors:
Peter G. Borden, Christopher Sean Olsen
Abstract: A photomask structure and method of etching is provided herein. In one embodiment, a photomask includes a translucent substrate and an opaque multi-layer absorber layer disposed over the substrate. The opaque multi-layer absorber layer comprises a self-mask layer disposed over a bulk absorber layer. The self-mask layer comprises one of nitrogenized tantalum and silicon-based materials (TaSiON), tantalum boron oxide-based materials (TaBO), or oxidized and nitrogenized tantalum-based materials (TaON). The bulk absorber layer comprises on of tantalum silicide-based materials (TaSi), nitrogenized tantalum boride-based materials (TaBN), or tantalum nitride-based materials (TaN). The self-mask layer has a low etch rate during the bulk absorber layer etch step, thereby acting as a hard mask.
Abstract: A method and system as described herein provides for detecting certain anomalies in a wafer. According to one aspect, these anomalies relate to defects or stress that can lead to wafer breakage before, during or after further wafer processing. According to other aspects, the method includes passing polarized light through a wafer and analyzing the transmitted light for any changes in polarization. According to additional aspects, the method includes analyzing the entire wafer in one image capturing operation. According to still further aspects, the light passed through the wafer is below the bandgap for a material such as silicon that comprises the wafer, so that substantially all light will be transmitted through rather than absorbed or reflected by the material. According to still further aspects, the detection operation can be rapid and automatic, so that it can be easily included in an overall processing sequence.
Abstract: Systems and methods are disclosed that include adjusting a pressure level of a sample gas in a testing chamber, for example, using a pressurized inert reference gas, and determining a composition of the adjusted sample gas. By adjusting the pressure level of the sample gas, the composition of the sample gas may be determined more accurately than otherwise possible. Numerous other aspects are disclosed.
Abstract: A computer program product that determines a polishing endpoint includes obtaining spectra from different zones on a substrate during different times in a polishing sequence, matches the spectra with indexes in a library and uses the indexes to determining a polishing rate for each of the different zones from the indexes. An adjusted polishing rate can be determined for one of the zones, which causes the substrate to have a desired profile when the polishing end time is reached.
Type:
Grant
Filed:
August 4, 2008
Date of Patent:
August 10, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Jeffrey Drue David, Dominic J. Benvegnu, Harry Q. Lee, Boguslaw A. Swedek, Lakshmanan Karuppiah
Abstract: Embodiments of methods of etching EUV photomasks are provided herein. In one embodiment, a method of etching an extreme ultraviolet photomask includes providing a photomask comprising, in order, a substrate, a multi-material layer, a capping layer, and a multi-layer absorber layer, the multilayer absorber layer comprising a self-mask layer disposed over a bulk absorber layer, wherein the self-mask layer comprises tantalum and oxygen and the bulk absorber layer comprises tantalum and essentially no oxygen; etching the self-mask layer using a first etch process; and etching the bulk absorber layer using a second etch process different than the first, wherein the etch rate of the bulk absorber layer is greater than the etch rate of the self-mask layer during the second etch process.
Type:
Grant
Filed:
September 15, 2006
Date of Patent:
August 10, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Banqiu Wu, Madhavi R. Chandrachood, Ajay Kumar
Abstract: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 ?m is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.
Type:
Grant
Filed:
August 24, 2009
Date of Patent:
August 10, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Dean Jennings, Haifan Liang, Mark Yam, Vijay Parihar, Abhilash Mayur, Aaron Hunter, Bruce Adams, Joseph Michael Ranish
Abstract: Processes for non-selectively forming one or more conformal silicon-containing epitaxial layers on recess corners are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of a non-selective epitaxial layer involves exposing a substrate in a process chamber to deposition gases including a silicon source such as silane and a higher order silane, followed by heating the substrate to promote solid phase epitaxial growth.
Type:
Grant
Filed:
October 18, 2007
Date of Patent:
August 10, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Zhiyuan Ye, Andrew Lam, Saurabh Chopra, Yihwan Kim
Abstract: A method of layer formation on a substrate with high aspect ratio features is disclosed. The layer is formed from a gas mixture comprising one or more process gases and one or more etch species. The one or more process gases react to deposit a material layer on the substrate. In conjunction with the material layer deposition, the etch species selectively remove portions of the deposited material layer adjacent to high aspect ratio feature openings, filling such features in a void-free and/or seam-free manner. The material layer may be deposited on the substrate using physical vapor deposition (PVD) and/or chemical vapor deposition (CVD) techniques.
Type:
Grant
Filed:
June 15, 2006
Date of Patent:
August 10, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Liang-Yuh Chen, Daniel A. Carl, Israel Beinglass
Abstract: A pulsed plasma system with pulsed reaction gas replenish for etching semiconductor structures is described. In an embodiment, a portion of a sample is removed by applying a pulsed plasma etch process. The pulsed plasma etch process comprises a plurality of duty cycles, wherein each duty cycle represents the combination of an ON state and an OFF state of a plasma. The plasma is generated from a reaction gas, wherein the reaction gas is replenished during the OFF state of the plasma, but not during the ON state. In another embodiment, a first portion of a sample is removed by applying a continuous plasma etch process. The continuous plasma etch process is then terminated and a second portion of the sample is removed by applying a pulsed plasma etch process having pulsed reaction gas replenish.
Type:
Grant
Filed:
February 22, 2007
Date of Patent:
August 10, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Tae Won Kim, Kyeong-Tae Lee, Alexander Paterson, Valentin N. Todorow, Shashank C. Deshmukh
Abstract: A sputtering cathode (1) for coating processes in a vacuum chamber (18) comprises one at least single-piece target plate (2) mounted on a metallic diaphragm (3). On the side of the diaphragm (3) facing away from the target plate (2) is disposed a cooling agent channel with an inflow line (9) and an outflow line (10) for a cooling agent and a hollow space (7) for at least one magnet system (5). The magnet system (5) is disposed in a supporting tub (6) sealed against the diaphragm (3) and not exposed to the cooling agent. The entire configuration is disposed on a supporting structure (12).
Abstract: Photovoltaic cells and methods for the manufacture of photovoltaic cells are described. Operative layers of the photovoltaic cell are deposited onto a superstrate having a plurality of spaced ramps, allowing for the individual cells to be connected in series with minimal loss of the efficiency due to dead space between the cells.
Abstract: Methods of forming a barrier layer for an interconnection structure are provided. In one embodiment, a method for forming an interconnect structure includes providing a substrate having a first conductive layer disposed thereon, incorporating oxygen into an upper portion of the first conductive layer, depositing a first barrier layer on the first conductive layer, and diffusing the oxygen incorporated into the upper portion of the first conductive layer into a lower portion of the first barrier layer. In another embodiment, a method for forming an interconnection structure includes providing a substrate having a first conductive layer disposed thereon, treating an upper surface of the first conductive layer with an oxygen containing gas, depositing a first barrier layer on the treated conductive layer, and depositing a second conductive layer on the first barrier layer while driving a portion of oxygen atoms from the treated conductive layer into the first barrier layer.
Abstract: A method of responding to voltage or current transients during processing of a wafer in a plasma reactor at each of plural RF power applicators and at the wafer support surface. For each process step and for each of the power applicators and the wafer support surface, the method includes determining an arc detection threshold lying above a noise level. The method further includes comparing each transient with the threshold determined for the corresponding power applicator or wafer support surface, and issuing an arc detect flag if the transient exceeds the threshold.
Abstract: A dual magnetron for plasma sputtering including a source magnetron and an auxiliary magnetron, each of which rotate about the center of the target at respective radii. The positions of the magnetron can be moved in complementary radial directions between sputter deposition and target cleaning. The magnetrons have different characteristics of size, strength, and imbalance. The source magnetron is smaller, stronger, and unbalanced source magnetron and is positioned near the edge of the wafer in sputter deposition and etching. The auxiliary magnetron is larger, weak, and more balanced and used for cleaning the center of the target and guiding sputter ions from the source magnetron in sputter deposition. Each magnetron may have its plasma shorted out in its radially outer position.
Type:
Grant
Filed:
October 27, 2006
Date of Patent:
August 3, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Cristopher M. Pavloff, Winsor Lam, Tza-Jing Gung, Hong S. Yang, Ilyoung Richard Hong
Abstract: A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion shower grid having plural elongate orifices oriented in a non-parallel direction relative to a surface plane of the ion shower grid.
Type:
Grant
Filed:
July 20, 2004
Date of Patent:
August 3, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Hiroji Hanawa, Tsutomu Tanaka, Kenneth S. Collins, Amir Al-Bayati, Kartik Ramaswamy, Andrew Nguyen
Abstract: A support for a substrate processing chamber comprises a fluid circulating reservoir comprising a channel having serpentine convolutions. A fluid inlet supplies a heat transfer fluid to the fluid circulating reservoir and a fluid outlet discharges the heat transfer fluid. In one version, the channel is doubled over to turn back upon itself.
Type:
Grant
Filed:
March 8, 2007
Date of Patent:
August 3, 2010
Assignee:
Applied Materials, Inc.
Inventors:
Andrew Nguyen, Wing Lau Cheng, Hiroji Hanawa, Semyon L. Kats, Kartik Ramaswamy, Yan Ye, Kwok Manus Wong, Daniel J. Hoffman, Tetsuya Ishikawa, Brian C. Lue
Abstract: Methods for forming connective elements on integrated circuits for packaging applications are provided herein. In some embodiments, a method of forming connective elements on an integrated circuit for flipchip packaging may include providing a resist layer on the integrated circuit; forming a plurality of holes through the resist layer; filling the plurality of holes with conductive material; and stripping at least a portion of the resist layer using a stripping solution containing acetic anhydride and ozone to expose the connective elements.