Patents Assigned to Applied Material
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Patent number: 7210988Abstract: Embodiments of a conditioning head for in-situ conditioning and/or cleaning a processing pad of a CMP, ECMP, or other processing system are provided. In one embodiment, the conditioning head includes a brush disposed in a central cavity. A cleaning fluid is provided through the central cavity of the conditioning head to a processing pad. The brush spins and moves laterally across the surface of the processing pad. The cleaning solution dispensed through the conditioning head dissolves by-products of the processing operation while the brush gently wipes the processing pad. A lip of the conditioning head retains the cleaning fluid and cleaning waste, thereby minimizing contamination of the area outside of the conditioning head. The cleaning waste is removed from the processing pad via passages formed near the outer periphery of the conditioning head.Type: GrantFiled: August 22, 2005Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Yan Wang, Stan D. Tsai, Yongqi Hu, Feng Q. Liu, Liang-Yuh Chen, Daxin Mao, Huyen Karen Tran, Martin S. Wohlert, Renhe Jia, Yuan A. Tian
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Patent number: 7210981Abstract: A method and apparatus for monitoring polishing pad conditioning mechanisms is provided. In one embodiment, a semiconductor substrate polishing system includes a rinse station, a polishing surface, a conditioning element, and a conditioning mechanism. The conditioning mechanism selectively positions the conditioning element over the polishing surface and over the rinse station. At least one sensor is provided and is configured to detect a first position and a second position of the conditioning element when disposed over the rinse station.Type: GrantFiled: November 14, 2005Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Alpay Yilmaz, Lakshmanan Karuppiah
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Patent number: 7210980Abstract: A polishing pad, polishing system, method of making a polishing pad and method of using a polishing pad. The polishing pad includes a polishing layer having a polishing surface, a backing layer with an aperture and a first portion that is permeable to liquid, and a sealant that penetrates a second portion of the backing layer adjacent to and surrounding the aperture such that the second portion is substantially impermeable to liquid. The aperture is positioned below a substantially fluid-impermeable element.Type: GrantFiled: August 26, 2005Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Bogdan Swedek, David J. Lischka, Jeffrey Drue David, Dominic J. Benvegnu
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Patent number: 7211144Abstract: A method of forming a tungsten nucleation layer using a sequential deposition process. The tungsten nucleation layer is formed by reacting pulses of a tungsten-containing precursor and a reducing gas in a process chamber to deposit tungsten on the substrate. Thereafter, reaction by-products generated from the tungsten deposition are removed from the process chamber. After the reaction by-products are removed from the process chamber, a flow of the reducing gas is provided to the process chamber to react with residual tungsten-containing precursor remaining therein. Such a deposition process forms tungsten nucleation layers having good step coverage. The sequential deposition process of reacting pulses of the tungsten-containing precursor and the reducing gas, removing reaction by-products, and than providing a flow of the reducing gas to the process chamber may be repeated until a desired thickness for the tungsten nucleation layer is formed.Type: GrantFiled: July 12, 2002Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Xinliang Lu, Ping Jian, Jong Hyun Yoo, Ken Kaung Lai, Alfred W. Mak, Robert L. Jackson, Ming Xi
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Patent number: 7210991Abstract: The present invention relates to an apparatus and method for polishing semiconductor substrates with improved throughput. Embodiments of the present invention eliminate load cups from a polishing system, hence improve throughput by reducing system footprint and substrate hand off. One embodiment provides an apparatus for polishing a substrate. The apparatus comprises a platen having a polishing pad supported thereon, a carrier head configured to hold the substrate and press the substrate against the polishing pad, and a retaining ring adapted to be attached to and detached from the carrier head, wherein the retaining ring is configured to receive the substrate while positioned on the polishing pad and detached from the carrier head.Type: GrantFiled: April 3, 2006Date of Patent: May 1, 2007Assignee: Applied Materials, Inc.Inventors: Shaun Van Der Veen, Hung Chih Chen
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Patent number: 7208249Abstract: We are able to significantly reduce variations in critical dimension from target for features in a patterned photoresist, where the patterned photoresist is generated during the fabrication of a reticle (photomask) to be used in semiconductor processing. The ability to maintain the targeted critical dimension of patterned photoresist features which were imaged using a direct write process depends upon the use of a photoresist binder resin system which provides a sufficiently dense structure to sterically hinder the movement of photoacid-labile groups after irradiation of such groups (writing of the pattern). As importantly, the photoacid groups which are used to generate the pattern need to be such that they are activated only at temperatures above about 70° C., and preferably at temperatures in the range of 110° C. to 150° C. Further improvement in uniformity of developed photoresist feature size across the reticle surface is achieved by controlling a combination of variables during development.Type: GrantFiled: September 30, 2002Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Melvin Warren Montgomery, Alex Buxbaum, Scott Edward Fuller, Cecilia Annette Montgomery
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Patent number: 7208325Abstract: A low-k dielectric layer having a composition of silicon, oxygen and carbon is removed from a wafer. The low-k dielectric layer is removed by exposing a surface of the low-k dielectric layer to an oxygen-containing gas to oxidized the surface. The oxidized surface is immersed in an etching solution having HF and H2SO4 to etch the low-k dielectric layer. The etched surface is exposed to at least one of (i) an etching solution having H2SO4 and H2O2, and (ii) an RF or microwave energized oxygen-containing gas, to remove the low-k dielectric layer from the wafer.Type: GrantFiled: January 18, 2005Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Hong Wang, Krishna Vepa, Paul V. Miller
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Patent number: 7208047Abstract: An apparatus through which a substrate may be transferred between a first chamber and a second chamber in which the first chamber is maintained at a high temperature relative to the ambient temperature of the second chamber. The apparatus comprises a passageway for receiving the substrate and a thermally isolating interface. The thermally isolating interface reduces heat transfer from the first chamber to the second chamber and allows for transfer of the substrate between the apparatus and the second chamber. The thermally isolating interface includes a hole having dimensions such that the substrate is transferrable through the thermally isolating interface.Type: GrantFiled: December 15, 2003Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Emanuel Beer, Kenneth E. Baumel
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Patent number: 7209055Abstract: An electrostatic deflector for a particle beam apparatus comprises opposing deflector plates that face one another across a particle beam gap and are electrostatically chargeable. Each deflector plate comprises its own voltage driver, which has a DAC and amplifier. Digital electronics receives an input digital code that expresses the complementary voltages to be applied to opposing deflector plates. When the input digital code is determined to provide a non-linear output response voltage from a DAC, the digital electronics provides an output digital code with a different digital code that provides a linear response from the DAC while providing the same differential voltage between the first and second deflector plates.Type: GrantFiled: October 3, 2005Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Scott C. Stovall, Richard L. Lozes
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Patent number: 7208425Abstract: Embodiments of the present invention provide methods, apparatuses, and devices related to chemical vapor deposition of silicon oxide. In one embodiment, a single-step deposition process is used to efficiently form a silicon oxide layer exhibiting high conformality and favorable gap-filling properties. During a pre-deposition gas flow stabilization phase and an initial deposition stage, a relatively low ratio of silicon-containing gas:oxidant deposition gas is flowed, resulting in formation of highly conformal silicon oxide at relatively slow rates. Over the course of the deposition process step, the ratio of silicon-containing gas:oxidant gas is increased, resulting in formation of less-conformal oxide material at relatively rapid rates during later stages of the deposition process step.Type: GrantFiled: March 3, 2006Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Nitin K. Ingle, Xinyua Xia, Zheng Yuan
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Patent number: 7207878Abstract: Embodiments of a polishing article for processing a substrate are provided. In one embodiment, a polishing article for processing a substrate comprises a fabric layer having a conductive layer disposed thereover. The conductive layer has an exposed surface adapted to polish a substrate. The fabric layer may be woven or non-woven. The conductive layer may be comprised of a soft metal and, in one embodiment, the exposed surface may be planar.Type: GrantFiled: January 8, 2005Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Yongqi Hu, Yan Wang, Alain Duboust, Feng Q. Liu, Antoine P. Manens, Siew S. Neo, Stan D. Tsai, Liang-Yuh Chen, Paul D. Butterfield, Yuan A. Tian, Sen-Hou Ko
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Patent number: 7208413Abstract: A method of forming a boride layer for integrated circuit fabrication is disclosed. In one embodiment, the boride layer is formed by chemisorbing monolayers of a boron-containing compound and one refractory metal compound onto a substrate. In an alternate embodiment, the boride layer has a composite structure. The composite boride layer structure comprises two or more refractory metals. The composite boride layer is formed by sequentially chemisorbing monolayers of a boron compound and two or more refractory metal compounds on a substrate.Type: GrantFiled: November 19, 2004Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Jeong Soo Byun, Alfred Mak
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Patent number: 7207871Abstract: A system for chemical mechanical polishing having a carrier head with pressurizeable chambers that can be configured into pressure zones is described. The system includes a carrier head with a membrane for contacting a substrate during polishing. Pressurizeable chambers behind the membrane are in communication with pressure inputs. The pressure inputs can each supply a different pressure to the pressurizeable chambers. Some of the pressurizeable chambers can be in communication with more than one pressure input. Zones of pressure can be arranged, where each zone includes one or more pressurizeable chambers. The zones can be configurable by altering the pressurizeable chambers that make up each zone.Type: GrantFiled: October 6, 2005Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Steven M. Zuniga, Hung Chih Chen, Thomas Brezoczky, Steven T. Mear
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Patent number: 7207766Abstract: A load lock chamber and method for transferring large area substrates is provided. In one embodiment, a load lock chamber suitable for transferring large area substrates includes a plurality of vertically stacked single substrate transfer chambers. The configuration of vertically stacked single substrate transfer chambers contributes to reduced size and greater throughput as compared to conventional state of the art, dual slot dual substrate designs. Moreover, the increased throughput has been realized at reduced pumping and venting rates, which corresponds to reduced probability of substrate contamination due to particulates and condensation.Type: GrantFiled: April 26, 2004Date of Patent: April 24, 2007Assignee: Applied Materials, Inc.Inventors: Shinichi Kurita, Wendell T. Blonigan, Yoshiaki Tanase
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Publication number: 20070087522Abstract: A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally-grown oxide trench liner.Type: ApplicationFiled: December 1, 2006Publication date: April 19, 2007Applicant: Applied Materials, Inc.Inventors: Srinivas Nemani, Shankar Venkataraman
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Publication number: 20070087515Abstract: The present invention generally relates to low compressive stress doped silicate glass films for STI applications. By way of non-limited example, the stress-lowering dopant may be a fluorine dopant, a germanium dopant, or a phosphorous dopant. The low compressive stress STI films will generally exhibit a compressive stress of less than 180 MPa, and preferably less than about 170 MPa. In certain embodiment, the STI films of the invention will exhibit a compressive stress less than about 100 MPa. Further, in certain embodiments, the low compressive stress STI films of the invention will comprise between about 0.1 and 25 atomic % of the stress-lowering dopant.Type: ApplicationFiled: October 17, 2005Publication date: April 19, 2007Applicant: Applied Materials, Inc.Inventors: Ellie Yieh, Lung-Tien Han, Anchuan Wang, Lin Zhang
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Publication number: 20070086931Abstract: In a first aspect, a first abatement apparatus is provided. The first abatement apparatus includes (1) an oxidation unit adapted to receive an effluent stream from a semiconductor device manufacturing chamber; (2) a first water scrubber unit adapted to receive the effluent stream from the oxidation unit; and (3) a catalysis unit adapted to receive the effluent stream from the first water scrubber unit. Numerous other aspects are provided.Type: ApplicationFiled: June 13, 2006Publication date: April 19, 2007Applicant: Applied Materials, Inc.Inventors: Sebastien Raoux, Brian Kingston, Mark Curry, Daniel Clark, Robbert Vermeulen, Belynda Flippo, Mark Holst, Steve Tsu, Kevin Lin, Monique Mcintosh
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Patent number: 7205228Abstract: A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.Type: GrantFiled: March 30, 2004Date of Patent: April 17, 2007Assignee: Applied Materials, Inc.Inventors: Deenesh Padhi, Srinivas Gandikota, Mehul Naik, Suketu A. Parikh, Girish A. Dixit
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Patent number: 7205153Abstract: Embodiments of the invention provide an analytical method and analytical reagent solutions for determining the concentration of electrolyte components, such as copper, acid and chloride constituents in an acid or basic metal plating bath using a chemical analyzer. Common methods for measuring the concentration of copper general require two reagent solutions/two steps. This invention provides a novel analytical reagent solution that simplifies the chelating, buffering, and cleaning functions of separate regent solutions required for measuring electrolyte concentration. This has the benefits of reducing chemical inventory and associated dispensing equipment, and thus reducing chemical consumption.Type: GrantFiled: April 11, 2003Date of Patent: April 17, 2007Assignee: Applied Materials, Inc.Inventor: Todd Alan Balisky
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Patent number: 7204886Abstract: A method and apparatus for performing multiple deposition processes is provided. In one embodiment, the apparatus includes a chamber body and a gas distribution assembly disposed on the chamber body. In one embodiment, the method comprises positioning a substrate surface to be processed within a chamber body, delivering two or more compounds into the chamber body utilizing a gas distribution assembly disposed on the chamber body to deposit a film comprising a first material, and then delivering two or more compounds into the chamber body utilizing a gas distribution assembly disposed on the chamber body to deposit a film comprising a second material. In one aspect of these embodiments, the gas distribution assembly includes a gas conduit in fluid communication with the chamber body, two or more isolated gas inlets equipped with one or more high speed actuating valves in fluid communication with the gas conduit, and a mixing channel in fluid communication with the gas conduit.Type: GrantFiled: November 13, 2003Date of Patent: April 17, 2007Assignee: Applied Materials, Inc.Inventors: Ling Chen, Vincent W. Ku, Mei Chang, Dien-Yeh Wu, Hua Chung