Patents Assigned to Applied Material
  • Patent number: 7081271
    Abstract: Embodiments of the invention relate to an apparatus and method of cyclical layer deposition utilizing three or more precursors. In one embodiment, the method includes providing at least one cycle of precursors to form a ternary material layer. Providing at least one cycle of precursors includes introducing a pulse of a first precursor, introducing a pulse of a second precursor, and introducing a pulse of a third precursor, wherein the pulses of two of the three precursors are introduced simultaneously or sequentially. In another embodiment, the method includes introducing a pulse of a first precursor, introducing a pulse of a second precursor, repeating the introduction of the first and the second precursors at least one time to form a binary material layer on the substrate surface, and introducing a pulse of a third precursor to form the ternary material layer.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: July 25, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Hua Chung, Ling Chen, Barry L. Chin
  • Publication number: 20060160374
    Abstract: Nano-porous low dielectric constant films are deposited utilizing materials having reactive by-products readily removed from a processing chamber by plasma cleaning. In accordance with one embodiment, an oxidizable silicon containing compound is reacted with an oxidizable non-silicon component having thermally labile groups, in a reactive oxygen ambient and in the presence of a plasma. The deposited silicon oxide film is annealed to form dispersed microscopic voids or pores that remain in the nano-porous silicon. Oxidizable non-silicon components with thermally labile groups that leave by-products readily removed from the chamber, include but are not limited to, limonene, carene, cymene, fenchone, vinyl acetate, methyl methacrylate, ethyl vinyl ether, tetrahydrofuran, furan, 2,5 Norbornadiene, cyclopentene, cyclopentene oxide, methyl cyclopentene, 2-cyclopentene-1-one, and 1-butene.
    Type: Application
    Filed: September 9, 2005
    Publication date: July 20, 2006
    Applicant: Applied Materials, Inc.
    Inventors: Dustin Ho, Derek Witty, Helen Armer, Hichem M'Saad
  • Publication number: 20060158240
    Abstract: A point of dispense temperature control apparatus for a track lithography system. The apparatus includes a first liquid source characterized by a first temperature and a first flow controller coupled to the first liquid source. The apparatus also includes a second liquid source characterized by a second temperature and a second flow controller coupled to the second liquid source. The apparatus further includes a mixing element coupled to the first flow controller and the second flow controller. The mixing element is adapted to provide a mixed stream characterized by a total flow volume and a temperature intermediate to the first temperature and the second temperature. The apparatus additionally includes a sensor coupled to the mixed stream, a point of dispense heat exchanger coupled to the mixed stream, and a control loop coupled to the sensor and at least one of the first flow controller or the second flow controller.
    Type: Application
    Filed: December 21, 2005
    Publication date: July 20, 2006
    Applicant: Applied Materials, Inc.
    Inventors: Sudhir Gondhalekar, Tetsuya Ishikawa
  • Patent number: 7078302
    Abstract: In one embodiment, the invention generally provides a method for annealing a doped layer on a substrate including depositing a polycrystalline layer to a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Yi Ma, Khaled Z. Ahmed, Kevin L. Cunningham, Robert C. McIntosh, Abhilash J. Mayur, Haifan Liang, Mark Yam, Toi Yue Becky Leung, Christopher Olsen, Shulin Wang, Majeed Foad, Gary Eugene Miner
  • Patent number: 7077973
    Abstract: Method and apparatus for etching a metal layer disposed on a substrate, such as a photolithographic reticle, are provided. In one aspect, a method is provided for processing a photolithographic reticle including positioning the reticle in a first orientation on a reticle support in a processing chamber, wherein the reticle comprises a metal photomask layer formed on an optically transparent substrate, and a patterned resist material deposited on the metal photomask layer, etching the metal photomask layer in the first orientation, positioning the reticle in at least a second orientation, and etching the metal photomask layer in the at least second orientation.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Alex Buxbaum, Bjorn Skyberg
  • Patent number: 7077725
    Abstract: In advanced electrolytic polish (AEP) method, a metal wafer (10) acts as an anodic electrodes and another metal plate (65) is used as a cathodic electrode. A voltage differential is applied to the anode and cathode under a predetermined anodic dissolution current density. This causes a reaction that provides a planarized surface on the metal wafers. Additives are included in the electrolyte solution (55) which adsorb onto the wafer surface urging a higher removal rate at higher spots and a lower removal rate at lower spots. Also, in another embodiment of the present invention is a pulsed-electrolytic process (260) in which positive and negative potentials are applied to the anodic and cathodic electrodes alternately, further encouraging surface planarization. AEP can be used either as a first step followed by a mechanical polish or a second step between initial CMP polish and a third step mechanical polish.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Lizhong Sun, Stan Tsai, Fritz Redeker
  • Patent number: 7078651
    Abstract: A substrate is initially positioned in the reaction chamber. One or more gases are introduced into the reaction chamber. A predetermined speed for translating a line of radiation is determined. Continuous wave electromagnetic radiation is then emitted from a continuous wave radiation source. The continuous wave electromagnetic radiation is subsequently focused into a line of radiation extending across the surface of the substrate. The line of radiation is then translated relative to the surface at the constant predetermined speed. The combination of the introduced gas/es and heat generated by the line of radiation causes the gas/es to react and deposit a layer on the surface of the substrate. Undesirable byproducts of the reaction are then flushed from the reaction chamber. This process is repeated until a layer having a predetermined thickness is formed on the surface of the substrate.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: July 18, 2006
    Assignee: Applied Materials Inc.
    Inventor: Dean Jennings
  • Patent number: 7077159
    Abstract: An apparatus 115 for processing a substrate 20, comprises an integrated pumping system 155 having a high operating efficiency, small size, and low vibrational and noise levels. The apparatus 115 comprises a chamber, such as a load-lock chamber 110, transfer chamber 115, or process chamber 120. An integrated and local pump 165 is abutting or adjacent to one of the chambers 110, 115, 120 for evacuating gas from the chambers. The pump has an inlet 170 connected to a chamber 110, 115, 120, and an outlet 175 that exhausts the gas to atmospheric pressure. Preferably, the pump 165 comprises a pre-vacuum pump or a low vacuum pump.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Peter Reimer, Pedram Sabouri, Dennis R. Smith
  • Patent number: 7079235
    Abstract: A method of reticle inspection, comprising generating a test reticle comprising a plurality of test pattern-features thereon; manufacturing a wafer using the reticle; and determining a transfer of at least one of said plurality of pattern features from said reticle to said wafer. Preferably, a neural network is trained using the determination. Preferably, a reticle is inspected by running detected defects through the neural network to determine if the detected defect has a consequence.
    Type: Grant
    Filed: May 6, 2002
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Yonatan Lehman
  • Patent number: 7078690
    Abstract: A method for production testing includes receiving a wafer including a semiconductor substrate and a non-conducting layer formed over the substrate, following etching of contact openings through the non-conducting layer to the substrate, the contact openings including an array of the contact openings arranged in a predefined test pattern in a test area on the wafer. An electron beam is directed to irradiate the test area, a specimen current flowing through the substrate responsive to the electron beam is measured. The specimen current is analyzed so as to assess a dimension of the contact openings.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Israel, Ltd.
    Inventors: Avi Simon, Alexander Kadyshevitch
  • Patent number: 7077721
    Abstract: Embodiments of a processing pad assembly for processing a substrate are provided. The processing pad assembly includes an upper layer having a processing surface and an electrode having a top side coupled to the upper layer and a bottom side opposite the top side. A first set of holes is formed through the upper layer for exposing the electrode to the processing surface. At least one aperture is formed through the upper layer and the electrode.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Yongqi Hu, Stan D. Tsai, Yan Wang, Feng Q. Liu, Shou-Sung Chang, Liang-Yuh Chen
  • Patent number: 7078711
    Abstract: A method that is sensitive to lattice damage (also called “primary method”) is combined with an additional method that independently measures one of two parameters to which the primary method is sensitive namely dose and energy. In some embodiments, the additional method is sensitive to dose, and in two such embodiments 4PP and SIMS are respectively used to measure dose (independent of energy). In other embodiments, the additional method is sensitive to energy, and in one such embodiment SIMS is used to measure energy (independent of dose). Use of such an additional method resolves an ambiguity in a prior art measurement by the primary method alone. The two methods are used in combination in some embodiments, to determine adjustments needed to match two or more ion implanters to one another or to a reference ion implanter or to a computer model.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Peter G Borden
  • Patent number: 7079740
    Abstract: Methods are provided for forming optical devices, such as waveguides, with minimal defect formation. In one aspect, the invention provides a method for forming a waveguide structure on a substrate surface including forming a cladding layer on the substrate surface, forming a core layer on the cladding layer, depositing an amorphous carbon hardmask on the core layer, forming a patterned photoresist layer on the amorphous carbon hardmask, etching the amorphous carbon hardmask, and etching the core material.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: July 18, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Laurent Vandroux, Herve Monchoix
  • Patent number: 7077264
    Abstract: According to a first aspect, a first conveyor system is provided that is adapted to deliver substrate carriers within a semiconductor device manufacturing facility. The first conveyor system includes a ribbon that forms a closed loop along at least a portion of the semiconductor device manufacturing facility. The ribbon is adapted to (1) be flexible in a horizontal plane and rigid in a vertical plane; and (2) transport a plurality of substrate carriers within at least a portion of the semiconductor device manufacturing facility. Numerous other aspects are provided, as are systems, methods and computer program products in accordance with these and other aspects.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: July 18, 2006
    Assignee: Applied Material, Inc.
    Inventors: Michael R. Rice, Robert B. Lowrance, Martin R. Elliott, Jeffrey C. Hudgens, Eric A. Englhardt
  • Publication number: 20060150913
    Abstract: A substrate processing system has a housing that defines a process chamber. A substrate holder disposed within the process chamber supports a substrate during substrate processing. A gas-delivery system introduces a gas into the process chamber. A pressure-control system maintains a selected pressure within the process chamber. A high-density plasma generating system forms a plasma having a density greater than 1011 ions/cm3 within the process chamber. A radio-frequency bias system generates an electrical bias on the substrate at a frequency less than 5 MHz. A controller controls the gas-delivery system, the pressure-control system, the high-density plasma generating system, and the radio-frequency bias system.
    Type: Application
    Filed: January 10, 2005
    Publication date: July 13, 2006
    Applicant: Applied Materials, Inc.
    Inventors: Rongping Wang, Canfeng Lai, Yuri Trachuk, Siamak Salimian
  • Patent number: 7075323
    Abstract: A method and system for testing one or more large substrates are provided. In one or more embodiments, the system includes a testing chamber having a substrate table disposed therein. The substrate table is adapted to move a substrate within the testing chamber in various directions. More particularly, the substrate table includes a first stage movable in a first direction, and a second stage movable in a second direction, wherein each of the stages moves in an X-direction, Y-direction or both X and Y directions. The system further includes a load lock chamber at least partially disposed below the testing chamber, and a transfer chamber coupled to the load lock chamber and the testing chamber. In one or more embodiments, the transfer chamber includes a robot disposed therein which is adapted to transfer substrates between the load lock chamber and the testing chamber.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Matthias Brunner, Shinichi Kurita, Wendell T. Blonigan, Edgar Kehrberg
  • Patent number: 7075165
    Abstract: A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Material, Inc.
    Inventors: Francisco A. Leon, Lawrence C. West, Yuichi Wada, Gregory L. Wojcik, Stephen Moffatt
  • Patent number: 7074714
    Abstract: We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Tony Chiang, Gongda Yao, Peijun Ding, Fusen E. Chen, Barry L. Chin, Gene Y. Kohara, Zheng Xu, Hong Zhang
  • Patent number: 7074298
    Abstract: The present invention is directed to the design of a plasma CVD chamber which provides more uniform conditions for forming thin CVD films on a substrate. In one embodiment, an apparatus for processing semiconductor substrates comprises a chamber defining a plasma processing region therein. The chamber includes a bottom, a side wall, and a dome disposed on top of the side wall. The dome has a dome top and having a side portion defining a chamber diameter. A top RF coil is disposed above the dome top. A side RF coil is disposed adjacent the side portion of the dome. The side RF coil is spaced from the top RF coil by a coil separation. A ratio of the coil separation to the chamber diameter is at least about 0.15, more desirably about 0.2–0.25.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: July 11, 2006
    Assignee: Applied Materials
    Inventors: Sudhir Gondhalekar, Tom K. Cho, Rolf Guenther, Shigeru Takehiro, Masayoshi Nohira, Tetsuya Ishikawa, Ndanka O. Mukuti
  • Patent number: 7074626
    Abstract: A method and apparatus for performing intra-tool monitoring and control within a multi-step processing system. The method monitors the processing of a workpiece as the workpiece is processed by independently operating processing tools and produces control parameters for the various independently operating processing tools to optimize the processing of the workpiece. More specifically, the apparatus provides a metrology station located between each of a plurality of semiconductor wafer processing tools such that measurements can be made on wafers as they are passed from one tool to another providing intra tool monitoring. The data collected by the metrology station is coupled to a metrology data analyzer, which determines whether any of the plurality of wafer processing tools should be adjusted to improve the processing of the overall wafer.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: July 11, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Suketu Parikh, Robin Cheung