Patents Assigned to Applied Materials
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Publication number: 20240332014Abstract: Molecular layer deposition (MLD) is used to provide conformal and uniform doping technology for HAR and reentrant structures. MLD is used to deposit a conformal carbon-based film that contains a doping element. Thermal annealing is then used to make the doping element diffuse into the semiconductor material. For HAR structures, a conformal layer is used with low temperature doping, precise control, and the carbon-based film can be easily removed during doping or after doping. The amount of doping can be controlled by changing the thickness of MLD carbon-based film.Type: ApplicationFiled: March 22, 2024Publication date: October 3, 2024Applicants: Applied Materials, Inc., National University of SingaporeInventors: Xinke Wang, Long Liu, Mark Saly, Bhaskar Jyoti Bhuyan, Jiecong Tang, John Sudijono
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Publication number: 20240332031Abstract: A method and system for etching high aspect ratio structures in a semiconducting processing chamber are disclosed herein. In one example, a method of patterning a substrate comprises etching the substrate to form a recess, depositing a passivation layer on sidewalls of the recess, treating the passivation layer, and etching the recess to a second depth. The substrate etch forms a recess to a first depth, the substrate having a mask layer disposed thereon. The treating of the passivation layer is for removal of a clogging material formed from an etch byproduct on the mask layer. The etching the recess to a second depth while maintaining a minimum variation of a recess sidewall width.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Feng QIAO, Hailong ZHOU, Qian FU, Sangjun PARK, Jayoung CHOI, Radhe AGARWAL, Tong LIU
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Publication number: 20240332027Abstract: Exemplary methods of semiconductor processing may include providing a first fluorine-containing precursor to a remote plasma system of a semiconductor processing chamber. The methods may include generating plasma effluents of the first fluorine-containing precursor in the remote plasma system. The methods may include providing plasma effluents of the first fluorine-containing precursor to a processing region of the semiconductor processing chamber. The methods may include providing a second fluorine-containing precursor to the processing region of the semiconductor processing chamber. A substrate including alternating layers of material may be disposed within the processing region. The alternating layers of material may include a silicon-and-germanium-containing material. The methods may include contacting the substrate with the plasma effluents of the first fluorine-containing precursor and with the second fluorine-containing precursor.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Anchuan Wang, Jiayin Huang, Kalpana Suen
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Publication number: 20240327300Abstract: Exemplary processing methods may include providing a powder to a processing region of a processing chamber. The methods may include providing one or more deposition precursors to the processing region. The methods may include generating plasma effluents of the one or more deposition precursors. The methods may include depositing a layer of material on the powder in the processing region. The layer of material may include a corrosion-resistant material. A temperature within the processing chamber is maintained at less than or about 700° C.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Nitin Deepak, Katherine Woo, Ryan Sheil, Juan Carlos Rocha-Alvarez, Jennifer Y. Sun
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Publication number: 20240332388Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.Type: ApplicationFiled: March 19, 2024Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Byeong Chan Lee, Benjamin Colombeau, Nicolas Breil, Ashish Pal, El Mehdi Bazizi, Veeraraghavan S. Basker, Balasubramanian Pranatharthiharan, Pratik B. Vyas, Gregory Costrini
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Publication number: 20240332075Abstract: Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include selectively depositing a first self-assembled monolayer (SAM) on the bottom of the gap; forming a barrier layer on the dielectric layer; selectively depositing a second self-assembled monolayer (SAM) on the barrier layer and on the bottom of the gap; treating the microelectronic device with a plasma to remove a first portion of the second self-assembled monolayer (SAM); selectively depositing a metal liner on the barrier layer on the sidewall; removing a second portion of the second self-assembled monolayer (SAM); and performing a gap fill process on the metal liner.Type: ApplicationFiled: March 22, 2024Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Jiajie Cen, Kevin Kashefi, Zhiyuan Wu, Yang Zhou, Yong Jin Kim, Carmen Leal Cervantes, Ge Qu, Zheng Ju
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Publication number: 20240332001Abstract: Exemplary methods of semiconductor processing may include providing a first precursor to a semiconductor processing chamber. A substrate may be disposed within a processing region of the semiconductor processing chamber. The substrate may define a feature. The methods may include contacting the substrate with the first precursor. The contacting may form a first portion of a silicon-carbon-and-nitrogen-containing material on the substrate. The methods may include providing a second precursor to the semiconductor processing chamber. The methods may include contacting the substrate with the second precursor. The contacting may form the silicon-carbon-and-nitrogen-containing material on the substrate. The silicon-carbon-and-nitrogen-containing material may be void free.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Lakmal C. Kalutarage, Bhaskar Jyoti Bhuyan, Mark J. Saly, Jeffrey W. Anthis
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Publication number: 20240334683Abstract: Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer (e.g., tungsten (W)) on a top surface of the insulating dielectric islands and on the bitline metal stack.Type: ApplicationFiled: March 22, 2024Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Tong Liu, Sony Varghese, Zhijun Chen, Balasubramanian Pranatharthiharan, Anand N. Iyer
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Publication number: 20240332003Abstract: Exemplary semiconductor processing methods may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber, the deposition precursors may be or include a tungsten-containing precursor. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the one or more deposition precursors in the processing region. The plasma may be at least partially formed by an RF power operating at less than or about 3,000 W and at a pulsing frequency less than or about 100,000 Hz. The methods may include forming a layer of material on the substrate. The layer of material may be or include a tungsten-containing material.Type: ApplicationFiled: March 29, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Qinghua Zhao, Guoqing Li, Rui Cheng
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Publication number: 20240332008Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-? dielectric layer on the interfacial layer, a dipole layer on the high-? dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-? dielectric layer.Type: ApplicationFiled: March 27, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Geetika Bajaj, Tianyi Huang, Hsin-Jung Yu, Yixiong Yang, Srinivas Gandikota, Chi-Chou Lin, Pei Hsuan Lin
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Publication number: 20240327988Abstract: A method of characterizing thermal processing chambers may include training a model using temperature rate-of-change data from existing thermal processing chambers. A supervised learning process may label the rate-of-change data based on deposition profiles on substrates. The trained model may be used to characterize another chamber to determine if the predicted performance will match the chambers used to train the model. An inert process using carrier gasses may be used to capture temperature data and derive rate-of-change data without requiring the actual deposition of an layer on the substrate. The rate-of-change data may be provided to the model, which may generate component-specific outputs that characterize how well the chamber is predicted to match either finger print condition of the chamber (match at different time) or match between different chambers.Type: ApplicationFiled: March 28, 2023Publication date: October 3, 2024Applicant: Applied Materials, Inc.Inventors: Zhepeng Cong, Ala Moradian
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Patent number: 12103135Abstract: An apparatus for chemical mechanical polishing includes a support for a polishing pad having a polishing surface, and an electromagnetic induction monitoring system to generate a magnetic field to monitor a substrate being polished by the polishing pad. The electromagnetic induction monitoring system includes a core and a coil wound around a portion of the core. The core includes a back portion, a center post extending from the back portion in a first direction normal to the polishing surface, and an annular rim extending from the back portion in parallel with the center post and surrounding and spaced apart from the center post by a gap. A width of the gap is less than a width of the center post, and a surface area of a top surface of the annular rim is at least two times greater than a surface area of a top surface of the center post.Type: GrantFiled: March 13, 2023Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: Hassan G. Iravani, Kun Xu, Denis Ivanov, Shih-Haur Shen, Boguslaw A. Swedek
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Patent number: 12106984Abstract: A method for determining processing chamber conditions using sensor data and a machine learning model is provided. The method includes receiving, by a processing device, sensor data that include chamber data indicating a state of an environment of a processing chamber processing a substrate according to a set of process parameters of a current process. The sensor data further include spectral data indicating optical emission spectra (OES) measurements of a plasma disposed within the processing chamber. The method further includes using the sensor data as input to a machine learning model and obtaining one or more outputs that indicate one or more chamber condition metrics. The method further includes determining a recovery status of a processing chamber based on the one or more chamber condition metrics. The method further includes causing a modification to a performance of the processing chamber based on the recovery status of the processing chamber.Type: GrantFiled: November 23, 2021Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventor: Pengyu Han
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Patent number: 12105504Abstract: First data associated with a first process performed for a first layer of a substrate is identified. The first layer is to be further processed according to a second process. The first data is provided as input to a machine learning model that is trained to predict metrology measurement values for layers of substrates at the manufacturing system. An amount of drift of a first set of metrology measurement values for the first layer following completion of the first process and/or the second process from target values is determined. Modifications to a recipe for the second process is determined in view of the determined amount of drift and second data associated with a second substrate layer that was previously processed at the manufacturing system. The second process is updated based on the determined one or more modifications.Type: GrantFiled: April 27, 2022Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventor: Pratik Champalal Kotcher
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Patent number: 12106958Abstract: Embodiments of the present disclosure generally relate to methods for cleaning a chamber comprising introducing a gas to a processing volume of the chamber, providing a first radiofrequency (RF) power having a first frequency of about 40 MHz or greater to a lid of the chamber, providing a second RF power having a second frequency to an electrode disposed in a substrate support within the processing volume, and removing at least a portion of a film disposed on a surface of a chamber component of the chamber. The second frequency is about 10 MHz to about 20 MHz.Type: GrantFiled: June 27, 2023Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: Anup Kumar Singh, Rick Kustra, Vinayak Vishwanath Hassan, Bhaskar Kumar, Krishna Nittala, Pramit Manna, Kaushik Alayavalli, Ganesh Balasubramanian
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Patent number: 12106936Abstract: A system may include a substrate stage, configured to support a substrate, where a main surface of the substrate defines a substrate plane. The system may include an ion source, including an extraction assembly that is oriented to direct an ion beam to the substrate along a trajectory defining a non-zero angle of incidence with respect to a perpendicular to the substrate plane. The system may include a radical source oriented to direct a radical beam to the substrate along a trajectory defining the non-zero angle of incidence with respect to a perpendicular to the substrate plane. The substrate stage may be further configured to scan the substrate along a first direction, lying with the substrate plane, while the main surface of the substrate is oriented within the substrate plane.Type: GrantFiled: June 26, 2023Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: Peter F. Kurunczi, Morgan Evans, Joseph C. Olson, Christopher A. Rowland, James Buonodono
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Patent number: 12108604Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.Type: GrantFiled: September 20, 2021Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: Jaesoo Ahn, Thomas Kwon, Mahendra Pakala
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Patent number: 12106943Abstract: A substrate holder assembly including a substrate platen, the substrate platen disposed to support a substrate at a substrate position, a halo ring, the halo ring being disposed around the substrate position, and an outer halo being disposed around the halo ring and defining a first aperture, wherein the outer halo is disposed to engage the halo ring, the halo ring being disposed at least partially within the first aperture, the halo ring defining a second aperture, concentrically positioned within the first aperture, wherein the outer halo and the halo ring are formed at least partially of silicon, silicon carbide, doped silicon, quartz, and ceramic.Type: GrantFiled: May 25, 2021Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: Jay R. Wallace, Simon Ruffell, Kevin R. Anglin, Tyler Rockwell, Christopher Campbell, Kevin M. Daniels, Richard J. Hertel, Kevin T. Ryan
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Patent number: 12106976Abstract: The present disclosure relates to a method and apparatus for cleaning a substrate. The method includes rotating a substrate disposed on a substrate support and spraying a front side of the substrate using steam through a front side nozzle assembly. A back side of the substrate is sprayed using steam through a back side dispenser assembly. A heated chemical is dispensed over the front side of the substrate.Type: GrantFiled: June 23, 2023Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: Jianshe Tang, Wei Lu, Haosheng Wu, Taketo Sekine, Shou-Sung Chang, Hari N. Soundararajan, Chad Pollard
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Patent number: 12104246Abstract: A method comprises depositing a first layer of aluminum oxide onto a surface of a chamber component via atomic layer deposition (ALD). The method further comprises depositing a second layer of yttrium oxide onto a surface of the chamber component via ALD, depositing a third layer of zirconium oxide onto the surface of the chamber component via ALD, and forming a corrosion and erosion resistant coating comprising a YZrxOy solid state phase of the second layer and the third layer, wherein x and y have values that are based on a number of repetitions of the atomic layer deposition process that are used to deposit the second layer and a number of repetitions of the atomic layer deposition process that are used to deposit the third layer.Type: GrantFiled: April 11, 2022Date of Patent: October 1, 2024Assignee: Applied Materials, Inc.Inventors: David Fenwick, Jennifer Y. Sun