Abstract: Subject matter disclosed herein may relate to fabrication of a correlated electron material (CEM) switch. In embodiments, processes are described in which conductive traces may be formed on or over an insulating material. Responsive to forming voids in the insulating material, localized portions of the conductive traces in contact with the voids may be exposed to gaseous oxidizing agents, which may convert the localized portions of the conductive traces to a CEM. In embodiments, an electrode material may be deposited within the voids to contact the localized portion of conductive trace converted to the CEM.

Abstract: A machine implemented method of communication between server and remote device, the method comprising: determining an availability and address of the remote device on a network for communication with the server; obtaining a public key attributed to the remote device; signing the public key attributed to the remote device with a private key of the server and so generating a digitally signed certificate to verify the ownership of the public key as the remote device; and transmitting the digitally signed certificate to the remote device.

Abstract: Memory address translation apparatus comprises a translation data store to store one or more instances of translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicating a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space; detector circuitry to detect whether a given virtual memory address to be translated lies in the range of virtual memory addresses defined by an instance of the translation data in the translation data store; in which the detector circuitry is configured, when the given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, to retrieve one or more further instances of the translation data; and translation circuitry to apply the

Abstract: A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

Abstract: A data processing system includes a memory system, a first processing element, a first address translator that maps virtual addresses to system addresses, a second address translator that maps system address to physical addresses, and a task management unit. A first program task uses a first virtual memory space that is mapped to a first system address range using a first table. The context of the first program task includes an address of the first table and is cloned by creating a second table indicative of a mapping from a second virtual address space to a second range of system addresses, where the second range is mapped to the same physical addresses as the first range until a write occurs, at which time memory is allocated and the mapping of the second range is updated. The cloned context includes an address of the second table.

Abstract: A system, apparatus and method are provided in which a range of virtual memory addresses and a copy of that range are mapped to the same first system address range in a data processing system until an address in the virtual memory address range, or its copy, is written to. The common system address range includes a number of divisions. Responsive to a write request to an address in a division of the common address range, a second system address range is generated. The second system address range is mapped to the same physical addresses as the first system address range, except that the division containing the address to be written to and its corresponding division in the second system address range are mapped to different physical addresses. First layer mapping data may be stored in a range table buffer and updated when the second system address range is generated.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of correlated electron materials comprising various impedance characteristics.

Abstract: A device comprising a storage array, the storage array comprising a first signal line and a second signal line, at least one correlated electron switch in electrical communication with the first signal line and the second signal line, and control circuitry for driving the correlated electron switch with at least one programming signal.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to integrated circuit fabrics including correlated electron switch devices having various impedance characteristics.

Abstract: A communications system and method provides power-saving while maintaining required protocol timing resolution. In a communication system that requires a high-frequency, high-precision, but high-power, clock source to meet timing requirements, selective disablement and re-enablement of the high-frequency clock provides for both timing precision and power reduction in the system.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material may be doped using dopant species derived from one or more precursors utilized to fabricate nearby structures such as, for example, a conductive substrate or a conductive overlay.

Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.

Abstract: Apparatus and methods of operating an electric motor are provided, comprising energizing a plurality of stator coils in sequence to rotate a rotor. Each said coil is energized with a repeating pulse sequence comprising at least a first portion and a second portion, the first and second portions repeating alternately to form the repeating pulse sequence. The first portion comprises a first pattern of pulses, each pulse in the first pattern having either a first polarity or second polarity, and at least two consecutive pulses in the first pattern having the same polarity. The second portion comprises a second pattern of pulses, the second pattern of pulses having the same pattern as said first pattern of pulses, but having inverted polarity with respect to said first pattern of pulses.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an unintentional change in the state of the non-volatile memory element.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.

Abstract: Described are methods, systems and devices for operation of correlated electron switch (CES) devices. A CES device may be placed in a conductive or low impedance state, or an insulative or high impedance state. A programming signal may be applied a CES device with a sufficiently high current to permanently place the CES device in the conductive or low impedance state.

Abstract: A virtual link buffer provides communication between processing threads or cores. A first cache is accessible by a first processing device and a second cache accessible by a second processing device. An interconnect structure couples between the first and second caches and includes a link controller. A producer cache line in the first cache stores data produced by the first processing device and the link controller transfers data in the producer cache line to a consumer cache line in the second cache. Each new data element is stored at a location in the producer cache line indicated by a store position or tail indicator that is stored at a predetermined location in the same cache line. Transferred data are loaded from a location in the consumer cache line indicated by a load position or head indicator that is stored at a predetermined location in the same consumer cache line.