Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.
Type:
Grant
Filed:
August 13, 2015
Date of Patent:
October 9, 2018
Assignee:
ARM Ltd.
Inventors:
Bal S. Sandhu, Cezary Pietrzyk, George McNeil Lattimore
Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.
Abstract: Broadly speaking, embodiments of the present technique provide a neuron for a spiking neural network, where the neuron is formed of at least one Correlated Electron Random Access Memory (CeRAM) element or Correlated Electron Switch (CES) element.
Type:
Application
Filed:
March 8, 2017
Publication date:
September 13, 2018
Applicant:
ARM LTD
Inventors:
Naveen SUDA, Vikas CHANDRA, Brian Tracy CLINE, Saurabh Pijuskumar SINHA, Shidhartha DAS
Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device.
Type:
Grant
Filed:
January 26, 2017
Date of Patent:
August 14, 2018
Assignee:
ARM Ltd.
Inventors:
Azeez Bhavnagarwala, Robert Campbell Aitken, Lucian Shifren
Abstract: According to one embodiment of the present disclosure, an apparatus is provided. The apparatus comprises a data input to receive a data signal. The apparatus further comprises a latching circuitry. The latching circuitry comprises a first Correlated Electron Switch (CES) element and a second CES element. The latching circuitry further comprises a control circuit coupled to the first CES element and the second CES element. The control circuit is configured to program impedance states of the first CES element and the second CES element based on the data signal.
Type:
Grant
Filed:
July 3, 2017
Date of Patent:
August 14, 2018
Assignee:
ARM Ltd.
Inventors:
Parameshwarappa Anand Kumar Savanth, James Edward Myers, Shidhartha Das
Abstract: Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.
Type:
Grant
Filed:
September 5, 2017
Date of Patent:
August 7, 2018
Assignee:
ARM Ltd.
Inventors:
Bal S. Sandhu, Cezary Pietrzyk, Robert Campbell Aitken, George McNeil Lattimore
Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of correlated electron materials comprising various impedance characteristics.
Type:
Grant
Filed:
March 20, 2017
Date of Patent:
July 31, 2018
Assignee:
ARM Ltd.
Inventors:
Carlos Alberto Paz de Araujo, Kimberly Gay Reid, Lucian Shifren
Abstract: An apparatus including a Correlated Electron Switch (CES) element and a programing circuit is provided. The programing circuit provides a programing signal to the CES element to program the CES element to an impedance state of multiple impedance states when a number of times the CES element has been programed is less than a threshold.
Type:
Grant
Filed:
March 31, 2016
Date of Patent:
July 24, 2018
Assignee:
ARM Ltd.
Inventors:
Lucian Shifren, Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu
Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to one or more barrier layers having various characteristics formed under and/or over and/or around correlated electron material.
Type:
Grant
Filed:
April 27, 2017
Date of Patent:
July 3, 2018
Assignee:
ARM Ltd.
Inventors:
Carlos Alberto Paz de Araujo, Kimberly Gay Reid, Lucian Shifren
Abstract: Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the load. In one implementation, a voltage and current of a generated read signal may be controlled so as to maintain a current impedance state of the load.
Abstract: Disclosed are methods, systems and devices for operation of dual non-volatile memory devices. In one aspect, a pair of non-volatile memory device coupled in series may be placed in complementary memory states any one of multiple memory states in write cycles by controlling a current and a voltage applied to terminals of the non-volatile memory device.
Type:
Grant
Filed:
December 21, 2016
Date of Patent:
June 26, 2018
Assignee:
ARM Ltd.
Inventors:
Azeez Bhavnagarwala, Robert Campbell Aitken
Abstract: Subject matter provided may relate to devices, such as conducting elements, which operate to place correlated electron switch elements into first and second impedance states. In embodiments, conducting elements are maintained to be at least partially closed continuously during first and second phases of coupling the CES elements between a common source voltage and a corresponding bitline.
Type:
Grant
Filed:
April 5, 2017
Date of Patent:
June 19, 2018
Assignee:
ARM Ltd.
Inventors:
Mudit Bhargava, Piyush Agarwal, Akshay Kumar, Glen Arnold Rosendale
Abstract: Disclosed are methods, systems and devices for operation of correlated electron switch (CES) devices. In one aspect, a CES device may be placed in any one of multiple impedance states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. In one implementation, a CES device may be placed in a high impedance or insulative state, or two more distinguishable low impedance or conductive states.
Abstract: A first plurality (201) of network nodes (120-123, 130-133) of a network (100) is associated with a first cryptographic keying material and the multicast IP address. A second plurality (202) of network nodes (120-123, 130-133) of the network (100) is associated with a second cryptographic keying material and the multicast IP address. The first cryptographic keying material has a different secret than the second cryptographic keying material.
Type:
Application
Filed:
July 6, 2016
Publication date:
June 14, 2018
Applicants:
TRIDONIC GMBH & CO KG, PHILIPS LIGHTING HOLDING B.V., ARM LTD
Inventors:
Abhinav Somaraju, Hannes Tschofenig, Sandeep Shankaran Kumar
Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an unintentional change in the state of the non-volatile memory element.
Type:
Grant
Filed:
October 14, 2016
Date of Patent:
June 12, 2018
Assignee:
ARM Ltd.
Inventors:
Shidhartha Das, Mudit Bhargava, Glen Arnold Rosendale
Abstract: Subject matter disclosed herein may relate to fabrication of layered correlated electron materials (CEMs) in which a first group of one or more layers may comprise a first concentration of a dopant species, and wherein a second group of one or more layers may comprise a second concentration of a dopant species. In other embodiments, a CEM may comprise one or more regions of graded concentration of a dopant species.
Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.