Abstract: A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.

Abstract: A de-interlacer includes recursive motion history map generating circuitry operative to determine a motion value associated with one or more pixels in interlaced fields based on pixel intensity information from at least two neighboring same polarity fields. The recursive motion history map generating circuitry generates a motion history map containing recursively generated motion history values for use in de-interlacing interlaced fields wherein the recursively generated motion history values are based, at least in part, on a decay function.

Abstract: A power management control circuit and method thereof includes a power register that contains a number of request tokens for at least one power consumption module. The number of request tokens represents a power adjust level of the at least one power consumption module. The power management control circuit and method thereof further includes a power controller coupled to the power register, wherein the power controller determines whether to adjust the power consumption module based on a comparison of a number of system tokens with the number of request tokens for the power consumption module. The power management control circuit and the method thereof further includes a token generator coupled to the power controller. The token generator generates the predetermined number of system tokens and a token valid signal for clearing an up token register and a down token register for each predetermined time interval.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: A software or hardware test system and method repeatedly obtains testing status of a plurality of test units in a group while the test units are testing hardware or software being executed on the test units. The system and method provides for display of the current testing status of the plurality of units of the group while the plurality of test units is performing software testing. In another embodiment, a test system and method compiles heuristic data for a plurality of test units that are assigned to one or more groups of test units. The heuristic data may include, for example, data representing a frequency of use on a per-test unit basis over a period of time, and other heuristic data. The test system and method evaluates job queue sizes on a per-group basis to determine whether there are under-utilized test units in the group and determines on a per-group of test unit basis whether a first group allows for dynamic reassignment of a test unit in the group based on at least the compiled heuristic data.

Abstract: The present disclosure relates to a thermal management apparatus used to manage temperature of components mounted to a circuit substrate, such as electronic or optical components. The apparatus includes a heat dissipation structure that includes at least one protrusion extending from a surface of the heat dissipation structure. A carrier structure is also included and engages with the heat dissipation structure. The carrier structure includes an aperture that receives the at least one protrusion. Additionally, the apparatus includes at least one biasing structure that is configured to allow movement of the heat dissipation structure relative to the carrier structure and provides a biasing force tending to move the heat dissipation structure and carrier structure together.

Abstract: An apparatus and method for processing pixel depth information eliminates stalling of data in a pixel pipeline, by performing late Z processing for one or more pixels currently in the pixel pipeline and early Z processing for one or more pixels entering the pixel pipeline. The apparatus and method also includes determining whether the late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The apparatus and method also includes solely performing early Z processing for subsequent pixels entering the pixel pipeline responsive to determining that late Z processing for the one or more pixels currently in the pixel pipeline has been completed. The methods and apparatus, facilitates concurrent processing of early and late Z data to avoid flushing portions of the pixel pipeline.

Abstract: The embodiments of the present invention are a method and apparatus to perform anti-aliasing using multi-sampling on a non-power-of-two pixel grid. Using the present invention with 6 sample multisampling gives the same visual antialiasing quality as 8 samples using a prior art technique but uses less memory. A non-power-of-two equally spaced sample from a conventional grid of size N×N, where N is 12 can be chosen using the present invention. A scan conversion to determine the set of pixels covered by a polygon is performed in two parts. According to one embodiment, the present invention can multiply and divide by “N” in order to multisample an image using samples per pixel chosen from a N×N sub-sample grid, where “N” is not necessarily a power of 2. The present invention performs the divide by “N” step, where the step is achieved using a quick divide by 3 or 12 technique.

Abstract: A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

Abstract: An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.

Abstract: To provide reduced power consumption of a co-processor, a low power dedicated memory is provided. During a low power state, a processing component of the co-processor is instructed to use the low power dedicated memory and a first memory device, normally used by the processing component, is thereafter operated in a reduced power mode for the duration of the low power state. Preferably, the low power dedicated memory has a storage capacity that is significantly less than the storage capacity of the first memory. When an operating state other than the low power state is detected, normal power consumption by the first memory is resumed and the co-processor is directed to use the first memory once again. In this manner, the present invention allows co-processors, and preferably graphics co-processors, to operate in a beneficial low power mode thereby reducing power consumption.

Abstract: A technique for processing at least one bad pixel occurring in an image sensing system is provided. Dynamic bad pixel detection is performed on a plurality of streaming pixels taking from at least one controlled image and value and coordinate information for each bad pixel is subsequently stored as stored bad pixel information. Thereafter, static bad pixel correction may be performed based on the stored bad pixel information. The stored bad pixel information may be verified based on histogram analysis performed on the plurality of streaming pixels. The technique for processing bad pixels in accordance with the present invention may be embodied in suitable circuitry or, more broadly, within devices incorporating image sensing systems.

Abstract: A device and method for controlling generation of a final pixel utilizes a conditional statement, referred to as an IF_NEIGHBOR statement, which when compiled, causes a programmable pixel shader to perform mip map texture lookups even if a pixel of interest does not meet the condition of the conditional statement. As such, any neighboring pixels needed for mip map selection have their associated shader code guaranteed to execute even though the pixel of interest may fail the conditional portion of the conditional statement. The device and method executes texture address calculations for pixels within a region and for pixels outside of a region but only those necessary to determine the mip map level corresponding to a pixel within the region. Execution of shader code for a current pixel is executed if any of the surrounding neighboring pixels meet the desired condition even if the current pixel does not meet the condition.

Abstract: Power consumption in a portable computer device that provides true-color simulation on a liquid crystal display can be realized by selectively operating a graphics controller that drives the LCD to selectively enable or disable true color simulation. Disabling dithering which provides true color simulation in an LCD, can significantly reduce power consumption by a portable computer device.

Abstract: Min-axis based mip map determination logic receives a plurality of texture space derivatives with respect to screen space for a given pixel and texel location and selects from a plurality of mip map levels a mip map level based on a min-axis without using a max-axis value and without using an amount of anisotropy. The plurality of mip map levels corresponds to mip map levels of a mip chain. The min-axis may be identified as the squares of the texture space derivatives with respect to either the x-axis or the y-axis of screen space. Selecting the mip map level based on the min-axis ensures that each texel of the selected mip map never maps to more than one pixel during texture mapping where the main texture is of sufficient resolution. Thus, using the mip map level based on the min-axis to fetch texture data from memory and render images results in few aliasing artifacts.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calculated tag distance is used to determine whether the pixels are outside a local image area defined about the uncached pixels. Pixels determined to be outside the local image area are replaced with the uncached pixels. The motion prediction cache can be organized as sets of cache lines and the method can be performed for each of the cache lines in one of the sets. The definition of the sets can be changed in response to cache performance. Similarly, the local image area can be redefined in response to cache performance.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: A processing unit of a system detects a fault condition associated with the co-processing unit and, upon detection, restores the processing unit using stored user context information. During normal operation, user context information used to execute operation commands are stored by the co-processing unit in memory and maintained after fault detection. A fault condition is detected when at least a portion of the processing unit is rendered non-operational due to a discharging electrostatic event. Fault conditions may be detected by receiving information by the co-processing unit indicative of a fault condition, or by checking at least one memory location associated with processing unit to determine if information stored therein indicates a fault condition. The co-processing unit returns the processing unit to a known, workable state by using the stored user context information to restore the pre-fault detection state information to the memory locations associated with the processing unit.