Abstract: Described are methods, devices, and systems for optimizing presentation of an image-bearing signal on a display device equipped with at least one adjustable picture control variable. The methods utilize, and the devices include, a picture control setting generator for determining different picture control settings, and an on-screen display generator for producing an on-screen display including multiple image cells (e.g., a mosaic). Each cell displays the same received image-bearing signal tuned according to a respective one of the different picture control settings. An end user selects among the different cells, choosing a cell that provides a preferred picture quality. In some embodiments, the picture control setting generator determines new picture control settings in response to the selected cell.

Abstract: A method and apparatus utilizes a three dimensional rendering engine to rotate an image based on user selected or otherwise determined screen orientation. A vertex coordinate transformation is defined for a rotated destination image. The source image is used as a texture for texture mapping during rendering operation to produce rotated image. In one embodiment, a separate set of software instructions is used for each orientation mode. Accordingly, a non-pixel by pixel based 3D rotation may be carried out using a 3D rendering engine to avoid a single parameter based seriatim pixel by pixel based orientation.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In a proposed embodiment, at least one heat pipe is used to transfer heat from the condensation portion of a vapor chamber to cool a bottom portion of a finned heat dissipation space and transfer the heat to a colder location on the heat fins. In another proposed embodiment, the water vapor chamber is placed in a heat sink and is adapted to thermally connect to at least one heat pipe.

Abstract: A demodulated multimedia signal is generated based on a captured handheld multimedia signal or a captured terrestrial multimedia signal where the handheld multimedia signal is formatted for reproduction on a handheld device and the terrestrial multimedia signal is formatted for reproduction on a computer system. The demodulated multimedia signal or a decoded multimedia signal (based on the demodulated multimedia signal) is transferred to a computer system for visual and/or audible reproduction on a computer system or for transmission to another computer system. The video information associated with the transferred signal is scaled by the computer system prior to display to match the display characteristics and capabilities of the computer system. The transferred signal may correspond to multiple channels of multimedia signals thereby enabling the display of multiple multimedia signals at the same time.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: The present invention is directed to a method, computer program product, and system for performing physics simulations on at least one graphics processor unit (GPU). The method includes the following steps. First, data representing physical attributes associated with at least one mesh are mapped into a plurality of memory arrays to set up of a linear system of equations that governs motion of the at least one mesh depicted in a scene. Then, computations are performed on the data in the plurality of memory arrays using at least one pixel processor to solve the linear system of equations for an instant of time, wherein modified data representing the solution to the linear system of equations for the instant of time are stored in the plurality of memory arrays.

Abstract: In a method and apparatus for generating a power supply voltage, an integrated circuit including an adaptive power supply voltage circuit is provided where a target signal is generated representing an ideal or approximated ideal performance characteristic of a functional block operating with the power supply voltage. A generated functional block test signal is generated representing the performance characteristic of the functional block under these conditions. The adaptive power supply voltage circuit compares the target signal with the generated functional block test signal and adjusts the power supply voltage continuously until the target signal and generated functional block test signal are substantially equal. When the target signal and generated functional block test signal are substantially equal, the power supply voltage is locked for subsequent use. By optimizing the power supply voltage, minimal power dissipation is provided.

Abstract: A method and apparatus for automated testing of display signals from video graphics circuitry includes capturing display signals that are provided from a processing device to the display device. The method and apparatus further includes converting the display signals into data acquisition signals, where a data acquisition signal includes a converted display signal having the display information contained therein wherein the data acquisition signal is in a form capable of being directly analyzed by a testing system. Furthermore, the method and apparatus includes providing the data acquisition signals to a test system that tests the display signals.

Abstract: Command handling logic receives a plurality of command requests and groups the plurality of command requests into one of a plurality of command tracking classifications to produce classification tagged command requests. The plurality of classification tagged command requests and corresponding plurality of command responses are communicated via a bus. Command classification tracking logic tracks the plurality of classification tagged command requests and a corresponding plurality of classification tagged command response to determine when there are no outstanding command requests associated with one of the plurality of command tracking classifications. There are no outstanding command requests associated with one of the plurality of command tracking classifications when the command classification tracking logic has received a number of classification tagged command responses equal to the number of sent classification tagged command requests associated with the same command tracking classification.

Abstract: A system and method for storing a multidimensional array of data, such as a two dimensional (2-D) array of video data, in a non-contiguous memory space. The system and method maps individually indexed elements of a multidimensional array of data from a source device into blocks of contiguous memory available in a destination memory system, even when the destination blocks are small and/or their size does not correlate in any way to the dimensions of a source buffer. In particular, the blocks of contiguous memory may be as small as a single element of the data indexed in the 2-D array.

Abstract: A method of deinterlacing interlaced fields of video for display in a progressive display device includes providing at least one candidate motion vector per scan line and determining, at least one final motion vector per scan line of interlaced video, for use in deinterlacing the interlaced fields, by iteratively changing the at least one candidate motion vector per scan line based on pixel intensities from each of a plurality of same polarity fields at locations along a single dimension.

Abstract: A method and a system for frame data to a frame sequential display device without using a frame buffer at the display device and while still maintaining the ability to use a standard interface capable of running at standard bandwidths is disclosed herein. A display system may be used to convert a multiple color frame to a plurality of single color component frames for sequential display on a display device. The display system includes a data system, a display controller, and a display device. The data system provides graphics data to the display controller. The display controller converts the graphics data into single color component frames and then transmits the single color component frames sequentially in sets of parallel data to the display device for display. The display device receives the sets of parallel data and converts the parallel data into sequential data. The sequential data is then output to a frame sequential display.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: To provide for the processing of priority data elements between a host processor and a co-processor that exchange such data elements using a queue, the host processor determines a priority of a data element received from an application. If the priority is higher than a lowest possible priority value, at least one lower priority data element within the queue may be identified and modified thereby temporarily removing it from the queue. When the priority data element is written into the queue a query packet is included that will cause the co-processor to return information regarding a last executed queued data element. Based on the returned information, the host processor can determine one or more unmodified data elements (uniquely corresponding to the one or more modified queued data elements) to be written into the queue in accordance with a sequence of the previously modified queued data elements.

Abstract: A technique for recording information in a battery operated device is provided such that quality level of the recorded information may be changed “on the fly.” In one embodiment, while persistently recording information at a first quality level, the battery operated device may, in response to an input a desire or need to change recording quality level, thereafter persistently record the information at a second quality level different from the first quality level, without interrupting the continuity of the recording session. In a presently preferred embodiment, the information being recorded may comprise video information or audio information. Subsequent inputs indicating the need to change recording quality level yet again may also be received thereby causing the battery operated device to persistently record the information at yet another quality level, which quality level may be the same as the first quality level.

Abstract: A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.

Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

Abstract: A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences.

Abstract: A data port operates to support symmetric PCI Express-type data transfers when in a first mode of operation. When in a second mode of operation, at least a portion of the data port connections are used to support an asymmetric PCI Express-type data transfer. The asymmetric data transfer is accommodated by supporting, with respect to the asymmetric data port, partial data lanes, thereby reducing the number of data channels implemented in a direction of the lower data rate transfer.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.