Abstract: A method for intelligently selecting a display image in a networked device is described. The method comprises receiving from a content provider image information and corresponding media data for display on a device. From the received image information, an image selection policy is determined. The image selection policy includes a level of specificity for an image to be to be displayed with the corresponding media data. An image for display is then selected for the corresponding text based on the determined image selection policy. The selected image is chosen from either (i) the memory cache of previously received images, or (ii) from the content provider.

Abstract: A current mobile multimedia signal time slice is captured using a mobile MM receiver in response to a current mobile multimedia stream-identifying command input. The current mobile multimedia signal time slice contains at least one portion of a currently selected mobile multimedia stream. At least one anticipated mobile multimedia time slice is selectively captured. The at least one anticipated mobile multimedia time slice contains at least one portion of a corresponding anticipated mobile multimedia stream.

Abstract: A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.

Abstract: A device includes a processor that is operative to process a data stream such as executable code, encoded video or other suitable data stream, and has a plurality of processor portions. The device further includes a power management controller coupled to the processor portions that controls power consumption of the processor portions based on application profile data associated with the data stream. The application profile data may be included with executable code or provided separately and may directly indicate usage/nonusage of portions of the processor or the data stream may have inherent application profile data in the header that indirectly identifies usage of the processor portions.

Abstract: A method and apparatus for interpolating image information obtains pixel information for a plurality of pixels surrounding a location of a pixel to be interpolated, whether the pixel is a missing pixel or an existing pixel whose color or intensity information is to be changed, and applies a gradient square tensor operation on a plurality of surrounding pixels to determine if the pixel to be interpolated is part of a geometric feature. If it is determined that the interpolated pixel is part of a geometric feature, such as a diagonal line or other suitable geometric feature, the method and apparatus uses pixel information from at least some of the surrounding pixels that are also determined to be the in geometric feature. This may be performed on a group of pixel basis and may include, for example, utilizing a block or kernel of pixels and a moving window of blocks of pixels to utilize the plurality of surrounding pixels.

Abstract: A method and apparatus for selectively charging a secondary voltage rail includes selectively and partially charging a secondary voltage rail using at least one soft start power gate switch and using an initial power control indicator. The partially charged secondary voltage rail is selectively charged, using at least one main power gate switch, based on the initial power control indicator and a detected voltage on the secondary voltage rail. When the initial power control indicator is in a state representative of an initial power up command and when the detected voltage is greater than or equal to a predetermined voltage level, at least one main power gate switch is closed thereby charging the secondary voltage rail.

Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.

Abstract: In a power management scheme for a power-consuming (e.g. electronic) device, one of multiple predefined operating parameter sets is selected. Each of the sets comprises multiple operating parameter values for the device. Examples of operating parameters include clock frequency or voltage for example. The selection may be responsive to the detection of an event which warrants a change in a current power consumption state of the device. Any operating parameter value in the selected set that would prevent the device from meeting current operating demands is modified to a new value. The new value may be taken from another operating parameter set. The modified set of parameters is applied to the device in order to change the current power consumption state of the device.

Abstract: A device includes a controller that is operative to dynamically control rendering quality of an output image when the device is in a reduced power mode based on data representing a desired runtime length of an application. Memory containing data representing quality of rendering control information may be utilized by the controller to control graphics processing circuitry to change a quality of graphics rendering based on the quality of rendering control information. The quality of control information may include, by way of example, and not limitation, data representing a number of vertices per object to use for rendering objects, a texture size to use per frame, a degree or type of anti-aliasing to employ, whether to use alpha blending, a tessellation level to employ, and playback frame rate information. A user interface may be employed that provides a selectable desired application runtime duration setting that is used when the device or portion of the device is in a low power mode.

Abstract: An electronic device having a processor powered by a power source may be operated by providing a plurality of program portions individually executable by the processor for performing the same computing function. Each program portion causes the processor to exhibit a different instantaneous power consumption profile while performing the computing function. A particular program portion is selected based on at least one characteristic of the power source and executed on the processor to perform the computing function.

Abstract: In an electronic device including a processor interface and a processor interconnected to the processor interface by a bus, activity on the bus is monitored and in response to inactivity, the processor interface is placed in a lower power consumption mode. While in the lower power consumption mode, processor requests to the processor interface are inhibited.

Abstract: A technique for adjusting or modifying content delivery to devices is provided, thereby offering a degree of power consumption control in such devices. The device can determine a need to modify power consumption, either in response to an input or via detection of an unfavorable power supply condition. In response, the device sends a request to an infrastructure for at least one reduced rate data stream. Because the at least one reduced rate data stream requires less processing power when undergoing decoding operations, the device subsequently consumes less power. In one embodiment of the present invention, the determination of the unfavorable power supply condition may be based on a configurable power condition profile. Furthermore, subsequent to receiving the at least one reduced rate data stream, the device may provide a request to the infrastructure for at least one increased rate data stream.

Abstract: A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads.

Abstract: A pseudo random number generator that generates a plurality of intermediate values, where each successive intermediate value is based, at least in part, on one of the succeeding intermediate values, where a final value based on a subset of the plurality of intermediate values. In application, the final value is based on performing a logical operation on the penultimate and last generated intermediate values.

Abstract: A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.

Abstract: An apparatus and method for facilitating program changes. The apparatus and method include a controller for detecting a change program request and for outputting change event data when a change event is detected. A non-active video information replacement module is coupled to the controller for receiving non-active video information and the change event data. When the replacement module receives change event data, a clear code generator generates clear code data that replaces non-active video information, and the non-active video information replacement module generates modified non-active video information. The modified non-active video information is provided to an output stage, whereupon the clear code data resets a non-active video information field within a display device, thereby preventing the display of erroneous information by a display within the output stage. Thereupon, clear code data is synthetically inserted within non-active video information upon the occurrence of a change event.

Abstract: The present disclosure relates to apparatus and methods for measurement of analog voltages in an integrated circuit. In particular, the apparatus includes an on-chip digital-to-analog converter configured to receive a variable digital input code and output a corresponding analog voltage corresponding to the variable digital input code. The apparatus also includes an on-chip comparator circuit configured to receive the analog voltage output by the digital-to-analog converter and a test analog voltage as inputs and to provide an output indicating the test analog voltage. Further, the apparatus includes an on-chip logic operative to determine the test analog voltage based on the output of the comparator circuit. A corresponding method is also disclosed.

Abstract: A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the input signal. The method and apparatus further includes a comparator coupled to receive an input strength indicator signal from the receiver and operative to generate a comparative strength signal based on the comparison of the input signal strength indicator signal and a reference strength signal. Furthermore, the method and apparatus includes a tuner coupled to the clock counter so the tuner receives the time value from the counter, and coupled to the comparator to receive the comparative strength signal from the comparator, whereupon the tuner then generates a tuning signal utilized for an iterative tuning process to fine tune a memory interface.

Abstract: The present disclosure relates to heat transfer thermal management device utilizing varied methods of heat transfer to cool a heat generating component from a circuit assembly or any other embodiment where a heat generating component can be functionally and operatively coupled. In an embodiment, the vapor configuration is modified to include fins that define a cross-flow heat exchanger there the vapor from the vapor chamber serves as the fluid in the vertical cross-flow in the heat exchanger and natural or forced cooling air serves as the horizontal cross-flow for the heat exchanger.

Abstract: A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.