Abstract: A method of video encoding is disclosed which is content adaptive. The encoding method is automatically adjusted to optimize the encoding, the adjusting depending on the content of the pictures being encoded. A system for implementing the method and a non-transitory computer-readable storage medium for storing instructions of the method are also disclosed.

Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: Methods and apparatus for facilitating motion estimation in video processing are provided. In one embodiment, search block is defined within one frame. A relative location of a corresponding block in another frame with respect to the search block is determined based on comparative searching at a predetermined granularity to produce a motion vector for the search block with a first precision. Correlation values are determined with respect to the search block for the corresponding block and for one block or more blocks defined at relative locations of less than the predetermined granularity with respect to the corresponding block in different directions. A refined motion vector for the search block with a second higher precision is determined based on the relative location of the block having a selected correlation value that is selected from among the determined correlation values.

Abstract: Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.

Abstract: A texture compression method is described. The method comprises splitting an original texture having a plurality of pixels into original blocks of pixels. Then, for each of the original blocks of pixels, a partition is identified that has one or more disjoint subsets of pixels whose union is the original block of pixels. The original block of pixels is further subdivided into one or more subsets according to the identified partition. Finally, each subset is independently compressed to form a compressed texture block.

Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.

Abstract: A method and apparatus to maximize video slice size is described herein. The method packs as many macroblocks as possible within a capped-size slice, while preserving user-defined quality constraints. The probability to conform to the maximum slice size constraint may be adjusted according to a user-defined parameter. The method may be integrated into a rate control process of a video encoder. The method predicts whether encoding a macroblock with a quantization parameter exceeds a current slice size constraint. It further predicts whether encoding a given number of macroblocks with a given configuration of quantization parameters exceeds the current slice size constraint. The method then proceeds to encode the current macroblock either on a condition that encoding the given number of macroblocks with the given configuration of quantization parameters falls below the size constraint of the current slice or after determining that a new slice is needed.

Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.

Abstract: Methods and apparatus that allow encoding of video data in pipelined encoder architectures with reduced encoding performance penalty. The methods and apparatus encode video data without the need to flush the data pipeline and re-encode macroblocks, thus saving time and resulting in an increase in the encoder's throughput. In one embodiment, macroblocks are encoded in a data pipeline to form a first video slice of a plurality of video slices. Once a macroblock overshoot condition occurs, the overshooting macroblock is determined and a second video slice is formed that includes at least one of the overshooting macroblock and the encoded macroblocks without re-encoding the included overshooting macroblock and encoded macroblocks. For example, a second video slice may be formed from the overshooting macroblock, and any remaining encoded macroblocks, that do not form the first video slice.

Abstract: A method for determining a macroblock (MB) coding mode for a current MB in a dependent view. A window around a co-located MB in a base view is determined, wherein the co-located MB is a MB in the base view having a same location as the current MB in the dependent view. A coding mode complexity value (CMCV) is determined for each MB in the window, wherein the CMCV is based on a coding mode used to encode the MB. Rate distortion optimization (RDO) is performed for the current MB using a reduced number of coding modes if a total CMCV for all MBs in the window is less than a threshold, or using all supported coding modes if the total CMCV for all MBs in the window is greater than the threshold. A coding mode for the current MB is determined based on the RDO results.

Abstract: An apparatus, computer readable medium, and method of event based dynamic power management. The method includes responding to receiving an indication of an event that is external to a hardware block engine by adjusting the power to the hardware block engine, if the event indicates that the power to the hardware block engine should be adjusted. The method may include receiving a second event that is external to the hardware block engine. The method may include determining whether or not the power should be adjusted to the hardware block engine based on the event and the second event. If it is determined that the power should be adjusted, then the power may be adjusted to the hardware block based on the event and second event. A method of monitoring a component and sending an indication of an event that the component will not require a hardware block engine is disclosed.

Abstract: Briefly, methods and apparatus to provide image content to, and display image content on, variable refresh rate displays with reduced input lag. The methods and apparatus allow for image tearing, or the displaying of image content from more than one video frame, when the render rate of a provided video frame falls outside the display refresh rate range of a variable refresh rate display when the display is refreshing with a previous frame (e.g. the display is in active refresh), thus reducing the input lag of the content of the provided video frame. The methods and apparatus may also prevent image tearing when the render rate of provided video frames is within the display refresh rate range of a display.

Abstract: A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture.

Abstract: In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (NVRAM), and an NVRAM-aware operating system. The NVRAM-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the NVRAM.

Abstract: Methods and apparatus for restricting access by one or more processors to an area of a secondary storage unit are presented herein. The methods and apparatus may comprise an independent programmable storage controller logic that divides a storage area of the secondary storage unit into at least a first area and a second area and controls usage of the areas as at least two virtual secondary storage units such that the processor(s) access the at least two virtual secondary storage units as if accessing at least two physical secondary storage units by selecting one of the at least two virtual secondary storage units as an active virtual secondary storage unit to provide the processor(s) access to the active virtual secondary storage unit based on a secondary storage unit configuration. Each virtual secondary storage unit may contain at least one region of which an access permission setting is modifiable.

Abstract: A virtualized DisplayPort (DP) configuration data (DPCD) for multi-stream transport (MST) logical DP end points and non-DP end points allows DPCD configuration for links within a DisplayPort topology which are not configurable using DPCD. A virtualized DPCD may configure a link to an internal display of a MST sink device or a non-DP display to receive data using a dynamic refresh rate (DRR), display stream compression (DSC), panel self-refresh (PSR) and other DPCD configurable features.

Abstract: Shader resources may be specified for input to a shader using a hierarchical data structure which may be referred to as a descriptor set. The descriptor set may be bound to a bind point of the shader and may contain slots with pointers to memory containing shader resources. The shader may reference a particular slot of the descriptor set using an offset, and may change shader resources by referencing a different slot of the descriptor set or by binding or rebinding a new descriptor set. A graphics pipeline may be specified by creating a pipeline object which specifies a shader and a rendering context object, and linking the pipeline object. Part or all of the pipeline may be validated, cross-validated, or optimized during linking.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: A method for coding a dependent view picture based on a reference picture includes selecting a reference picture from a base view picture list if a metric of intra macroblocks in an evaluated picture is greater than a first threshold, selecting a reference picture from a dependent view picture list if a metric of skipped macroblocks in the evaluated picture is greater than a second threshold, and coding a dependent view picture using the selected reference picture. An application-controlled weighting mechanism may be used if both of the thresholds are not met.