Abstract: Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.

Abstract: Coherent memory copy logic is operative to copy data from a source memory location to a destination memory location and duplicate a write request to a source memory region to produce a duplicated write request. Coherent memory copy logic is also operative to execute the duplicated write request to copy content from the external memory region to the destination memory region. Power to the source memory can then be reduced to save power while the internal memory is being used. Accordingly, a type of “hardware memory mover” does not require the use of any complex software synchronization and does not result in any service interruption during a memory move. The coherent memory copy logic reallocates the application memory space from, for example, external memory to internal memory within a chip in a manner that is transparent to the application software and the user. Corresponding methods are also set forth.

Abstract: A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.

Abstract: A power converter for a load with varying power requirements dynamically adjusts its supply voltage to the load so as to track the radio frequency (RF) envelope of the signal being carried by the load. The supply voltage can be provided by a multiple-output charge pump providing multiple output voltage levels concurrently, and a switch to provide a selected one of the different output voltage levels as the supply voltage to the load. A controller controls the switch to dynamically modify the voltage level selected for output as the supply voltage such that the supply voltage tracks the RF envelope of the signal being carried by the load. As the switching losses of transistors of the power converter may exceed the power savings achieved through envelope tracking, the power converter employs a peak following frequency divider circuit that limits the switching frequency of the power converter to a threshold frequency.

Abstract: A system for decoding video data includes a processing unit. The processing unit includes a plurality of processing pipelines and a driver. The driver includes a decoder configured to generate a plurality of intermediate control maps containing control information including an indication of which macro blocks or portions of macro blocks may be processed in parallel in the plurality of processing pipelines.

Abstract: A wireless display system and method decompresses a compressed video stream, such as obtained from suitable video sources such as a cable modem, DVD player or other suitable source, to produce a decompressed video stream locally. The decompressed video stream, such as frames, is stored in a local frame buffer, such as an on-chip frame buffer, system memory, or any other suitable memory. The system and method then recompresses the stored frames and wirelessly transmits the recompressed frames using a short range wireless transmitter, such as a radio frequency-based short range transmitter, an infrared short range wireless transmitter, or any other suitable short range transmitter that may provide, for example, local area networking.

Abstract: A communications device, a communications system, a method, and a computer readable storage device having a non-transitory computer program stored thereon, are disclosed. All of these are directed to reducing power consumption associated with processing of audio-video (AV) content, such as streaming video.

Abstract: Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.

Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: A virtualized DisplayPort (DP) configuration data (DPCD) for multi-stream transport (MST) logical DP end points and non-DP end points allows DPCD configuration for links within a DisplayPort topology which are not configurable using DPCD. A virtualized DPCD may configure a link to an internal display of a MST sink device or a non-DP display to receive data using a dynamic refresh rate (DRR), display stream compression (DSC), panel self-refresh (PSR) and other DPCD configurable features.

Abstract: Generally, an apparatus and a method for encoding multiview video downscale two views of the multiview video, determine a shift between the downscaled views, and encode one the two views using the shift.

Abstract: To apportion desired video processing between a video source device and a video sink device, at one of the devices, and based upon an indication of video processing algorithms of which the other device is capable and an indication of video processing algorithms of which the one device is capable, a set of video processing algorithms for achieving desired video processing is identified. The identified set of video processing algorithms is classified into a first subset of algorithms for performance by the other device and a second subset of algorithms for performance by the one device. At least one command for causing the other device to effect the first subset of video processing algorithms is sent. The one device may be configured to effect the second subset of algorithms.

Abstract: Disclosed is a low-complexity and yet efficient lossy method to compress distortion information for motion estimation, resulting in significant reduction in needed storage capacity. A system for implementing the method and a computer-readable medium for storing the method are also disclosed. The method includes determining and storing a distortion value for each trial motion vector in a plurality of trial motion vectors. Each trial motion vector specifies a position of a search region relative to a reference frame. The method further includes compressing each of the distortion values as a fixed number of bits based upon a minimum distortion value amongst the stored distortion values, and re-storing each compressed distortion value in place of its uncompressed value.

Abstract: In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

Abstract: Briefly, methods and apparatus provide image content to, and display image content on, displays with a variable refresh rate that reduce frame delays and avoid display image flickering problems. In one example, the methods and apparatus are operative to vary a display's refresh rate by varying a current frame's vertical blanking period by re-providing the current frame for display prior to providing a new frame for display. In this fashion, the displaying of a new frame may be advanced by assuring that a new frame can be provided for display as soon as it has been rendered and available for display. In addition, by re-providing the current frame for display prior to providing a new frame for display, new frames may be provided for display at rates within a safe rate range such that display image flickering issues are avoided or reduced.

Abstract: Graphics rendering settings in a computer system are adjusted when an activity level on a bus meets a trigger condition. The graphics rendering settings of the system are returned to a previous level when the bus activity drops below a threshold. The trigger condition may be related to bandwidth usage on the bus or latency of data sent over the bus.

Abstract: Apparatus include(s) a package having a load, and methods of making an electronic circuit include disposing the package on a printed circuit board. The apparatus include(s) an integrated conducting element and inductive element disposed on the printed circuit board and connected to the package that includes the load. The methods include disposing the integrated conducting element and inductive element on the printed circuit board so that the integrated conducting element and inductive element connects to the package. The integrated conducting element and inductive element includes a conducting element integral with an inductive element. The inductive element includes a magnetic element and a winding element. The winding element comprises a portion of the conducting element.

Abstract: Techniques for performing DC to DC power conversion in switch-mode converter circuits include combinations of dynamic switch shedding, phase shedding, symmetric phase circuit topologies, and asymmetric phase circuit topologies. In at least one embodiment of the invention, a method of operating a power converter circuit includes operating a first phase switch circuit portion using a first number of switch devices when the power converter circuit is configured in a first mode of operation. The first number is greater than zero. The method includes operating the first phase switch circuit portion using the first number of switch devices when the power converter circuit is configured in a second mode of operation. The method includes operating a second phase switch circuit portion using a second number of switch devices when the power converter circuit is configured in the second mode of operation. The second number is greater than the first number.