Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.

Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.

Abstract: An electronic device that includes a decompression engine that includes N decoders and a decompressor decompresses compressed input data that includes N streams of data. Upon receiving a command to decompress compressed input data, the decompression engine causes each of the N decoders to decode a respective one of the N streams from the compressed input data separately and substantially in parallel with others of the N decoders. Each decoder outputs a stream of decoded data of a respective type for generating commands associated with a compression standard for decompressing the compressed input data. The decompressor next generates, from the streams of decoded data output by the N decoders, commands for decompressing the data using the compression standard to recreate the original data. The decompressor next executes the commands to recreate the original data and stores the original data in a memory or provides the original data to another entity.

Abstract: A technique for determining an adaptive quantization parameter offset for a block of encoded video includes obtaining a rate control factor for the quantization parameter, determining a content-based quantization parameter factor for the quantization parameter, determining an adaptive variance based quantization offset based on content-based quantization parameter factors for a frame prior to the current frame, and combining the rate control factor, the content-based quantization parameter factor, and the adaptive offset to generate the quantization parameter.

Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.

Abstract: A technique for detecting a glitch in an image is provided. The technique includes providing an image to a plurality of individual classifiers to generate a plurality of individual classifier outputs and providing the plurality of individual classifier outputs to an ensemble classifier to generate a glitch classification.

Abstract: A graphics processing unit (GPU) of a processing system transmits pixel data for a frame to a display in a compressed burst, so that the pixel data is communicated at a rate that is higher than the rate at which the display scans out the pixel data to refresh the frame at a display panel. By transmitting pixel data for the frame in a compressed burst, the GPU shortens the time spent transmitting the pixel data and extends the time before the next frame of pixel data is to be transmitted. During the extended time before the next frame of pixel data is to be transmitted, the GPU saves power by placing portions of the processing system in a reduced power mode.

Abstract: Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.

Abstract: A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a sparsity of the feature maps and store the plurality of different feature maps in the memory.

Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.

Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.

Abstract: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.

Abstract: An apparatus includes a processor, a sleep state duration prediction module, and a system management unit. The sleep state duration prediction module is configured to predict a sleep state duration for component of the processing device. The system management unit is to transition the component into a sleep state selected from a plurality of sleep states based on a comparison of the predicted sleep state duration to at least one duration threshold. Each sleep state of the plurality of sleep states is a lower power state than a previous sleep state of the plurality of sleep states.

Abstract: A method and apparatus for adjusting a display includes receiving a video stream. The video stream is analyzed for one or more environmental conditions. Based upon the analysis, a portion of the display is adjusted.

Abstract: A disclosed technique includes prefetching display data into a cache memory, wherein the display data includes data to be displayed on a display during a memory black-out period for a memory; triggering the memory black-out period; and during the black-out period, reading from the cache memory to obtain data to be displayed on the display.

Abstract: A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form an anti-resonance tuning circuit has a first branch including a first inductance coupled to one of an IC die positive power supply conductor and an IC die negative power supply conductor, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

Abstract: A receiver circuit includes an analog front end and a non-linear equalizer. The analog front end including a super source follower (SSF) amplifier having a first input terminal adapted to couple to a transmission line to receive an input signal referenced to a first voltage level, a second input adapted to receive a reference voltage, and first and second output terminals adapted to provide an amplified signal referenced to a second voltage level. The non-linear equalizer coupled to receive an output signal of the analog front end and compensate for inter-symbol interference at a data rate of at least 14 Gbps. The SSF amplifier includes transistors having relative sizes selected to provide a frequency response of the SSF amplifier with a peak at a frequency approximately ? of the data rate.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.

Abstract: Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.