Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: A structure and associated method to implement encryption/decryption under the Data Encryption Standard (DES). Several additional instructions are included in the instruction set of a general purpose microprocessor to operate in conjunction with hardware included in a data path of the general purpose microprocessor. The additional instructions perform a portion of the DES algorithm, in particular, a portion of a DES round. The state information used at each step of the encryption portion of the DES algorithm is provided in various general purpose registers of the general purpose microprocessor. In one embodiment, all sixteen subkeys are selected prior to the DES step in the general processor after a DES key is known. In another embodiment, each subkey is selected during the round it is used. In yet another embodiment, each subkey is selected during the round it is used, as part of an additional instruction executed by the general purpose microprocessor.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calculated tag distance is used to determine whether the pixels are outside a local image area defined about the uncached pixels. Pixels determined to be outside the local image area are replaced with the uncached pixels. The motion prediction cache can be organized as sets of cache lines and the method can be performed for each of the cache lines in one of the sets. The definition of the sets can be changed in response to cache performance. Similarly, the local image area can be redefined in response to cache performance.

Abstract: A comminution apparatus for reducing a particle size of a material includes a cutting chamber defining an interior volume, wherein the cutting chamber includes first and second member forming an angle therebetween. Each of the first and second members include a plurality of slots therethrough providing access to the interior volume. The apparatus further includes a rotatable arbor disposed outside the interior volume of the cutting chamber and supporting a plurality of toothed blades thereon. During rotation of the arbor a portion of each of the blades enters an interior volume of the cutting chamber through the slots in the first member and exits the interior volume of the cutting chamber through the slots in the second member. The comminution apparatus may be used to process various feed materials to desired sizes, and is particularly useful for reducing the size of materials otherwise difficult to cut to small size.

Abstract: A target pixel and surrounding pixels corresponding to the target pixel are obtained from a digitally represented image. A bilateral high pass filtering kernel is determined based at least in part upon the target pixel and the surrounding pixels. A high pass spatial filtering kernel is provided and multiplied with the high pass photometric filtering kernel to provide a bilateral high pass filtering kernel. The resulting bilateral high pass filtering kernel is thereafter applied to the target pixel and the surrounding pixels to provide a filtered pixel. When it is desirable to combine noise filtering capabilities with sharpening capabilities, the bilateral high pass filter of the present invention may be combined with a bilateral low pass filtering kernel to provide a combined noise reduction and edge sharpening filter. The present invention may be advantageously applied to a variety of devices, including cellular telephones that employ image sensing technology.

Abstract: Embodiments of the present invention provide methods of processing nickel-titanium alloys including from greater than 50 up to 55 atomic percent nickel to provide a desired austenite transformation temperature and/or austenite transformation temperature range. In one embodiment, the method comprises selecting a desired austenite transformation temperature, and thermally processing the nickel-titanium alloy to adjust an amount of nickel in solid solution in a TiNi phase of the alloy such that a stable austenite transformation temperature is reached, wherein the stable austenite transformation temperature is essentially equal to the desired austenite transformation temperature.

Abstract: At least one illuminant white point estimate is determined in a color space having radially defined saturation based on a reference image. A chromatic adaptation correction vector (CACV) is determined based on the at least one illuminant white point estimate. Corrected pixels are obtained by applying the CACV (preferably in a cone response color space using a correction matrix based on the CACV) to uncorrected image pixels corresponding to a target image, which may comprise the reference image or another image.

Abstract: A processing unit of a system detects a fault condition associated with the co-processing unit and, upon detection, restores the processing unit using stored user context information. During normal operation, user context information used to execute operation commands are stored by the co-processing unit in memory and maintained after fault detection. A fault condition is detected when at least a portion of the processing unit is rendered non-operational due to a discharging electrostatic event. Fault conditions may be detected by receiving information by the co-processing unit indicative of a fault condition, or by checking at least one memory location associated with processing unit to determine if information stored therein indicates a fault condition. The co-processing unit returns the processing unit to a known, workable state by using the stored user context information to restore the pre-fault detection state information to the memory locations associated with the processing unit.

Abstract: A method for displaying images on multiple monitors with different refresh rates is disclosed. To prevent screen tearing, the surface containing image data is not released when the access by the master monitor is completed until the slave monitor or monitors finish access. To synchronize images with a predefined playback speed, the surface containing a new image received from the application is not flipped onto the screens until receiving a predefined synchronization indicator.

Abstract: The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4×4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.

Abstract: In a method and apparatus for generating a power supply voltage, an integrated circuit including an adaptive power supply voltage circuit is provided where a target signal is generated representing an ideal or approximated ideal performance characteristic of a functional block operating with the power supply voltage. A generated functional block test signal is generated representing the performance characteristic of the functional block under these conditions. The adaptive power supply voltage circuit compares the target signal with the generated functional block test signal and adjusts the power supply voltage continuously until the target signal and generated functional block test signal are substantially equal. When the target signal and generated functional block test signal are substantially equal, the power supply voltage is locked for subsequent use. By optimizing the power supply voltage, minimal power dissipation is provided.

Abstract: A thermal management device for a circuit substrate having at least a first heat generating component and at least a second heat generating component, the thermal management device includes a first thermal spreader and a second thermal spreader. The second thermal spreader is mountable to the circuit substrate to thermally couple with the second heat generating component. Additionally, the second thermal spreader is adapted to couple to the first thermal spreader to thermally couple the first thermal spreader to the first heat generating component when the second thermal spreader is mounted to the circuit substrate. The thermal management device also includes a bias device that is coupled to the first thermal spreader and the second thermal spreader and is adapted to maintain the thermal coupling between the first thermal spreader and the first heat generating component when the second thermal spreader is mounted to the circuit substrate.

Abstract: A method for refining and casting metals and metal alloys includes melting and refining a metallic material and then casting the refined molten material by a nucleated casting technique. The refined molten material is provided to the atomizing nozzle of the nucleated casting apparatus through a transfer apparatus adapted to maintain the purity of the molten refined material. An apparatus including a melting and refining apparatus, a transfer apparatus, and a nucleated casting apparatus, in serial fluid communication, also is disclosed.

Abstract: An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.

Abstract: To receive new services including audio or video content for presentation by a cable-compatible digital television or other digital audio/video receiver, a module may be connected to the HOST-POD interface of the digital television. The module has a receiver for receiving audio or video content in a first compression format, a transcoder for converting said audio or video content from the first compression format into a second, different compression format, and a controller for transmitting the audio or visual content in the second compression format to the digital television over a HOST-POD interface. By using such a module, front-end components of the digital television may be bypassed while back-end components may be utilized to decompress and present the content. The module may be a PC card or smart card for example.

Abstract: A multiphase clock generating circuit includes a multiphase clock generator that produces a plurality of multiphase output signals at a first frequency and a multiphase divider with delayed reset control. The multiphase divider with delayed reset control is operatively coupled to receive the plurality of multiphase output signals at the first frequency and further operative to produce a plurality of multiphase output signals at a second frequency based on reset control information. As a result, an interface can be supplied with and switch between multiphase clock at different frequencies within a short amount of time with reduced power consumption and circuit area.