Abstract: The embodiments of the present invention are a method and apparatus to perform anti-aliasing using multi-sampling on a non-power-of-two pixel grid. Using the present invention with 6 sample multisampling gives the same visual antialiasing quality as 8 samples using a prior art technique but uses less memory. A non-power-of-two equally spaced sample from a conventional grid of size N×N, where N is 12 can be chosen using the present invention. A scan conversion to determine the set of pixels covered by a polygon is performed in two parts. According to one embodiment, the present invention can multiply and divide by “N” in order to multisample an image using samples per pixel chosen from a N×N sub-sample grid, where “N” is not necessarily a power of 2. The present invention performs the divide by “N” step, where the step is achieved using a quick divide by 3 or 12 technique.

Abstract: A Force/Torque (FT) sensor includes memory for storing calibration data associated with the FT sensor. Force and torque analog signals are output to a data acquisition (DAQ) system. The digital calibration data is output to the DAQ system as a digital bitstream comprising a series of predetermined voltage levels driven for predetermined durations. The DAQ system interprets the series of voltage levels on the calibration input as a digital bitstream, receives and quantizes the force/torque signals, and calibrates the force/torque signals using the calibration data. Alternatively, the calibration signals may be routed to a standard serial port on the DAQ system. For small form factor FT sensors, the calibration data may be stored in an associated power supply unit.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: A method of deinterlacing interlaced fields of video for display in a progressive display device includes providing at least one candidate motion vector per scan line and determining, at least one final motion vector per scan line of interlaced video, for use in deinterlacing the interlaced fields, by iteratively changing the at least one candidate motion vector per scan line based on pixel intensities from each of a plurality of same polarity fields at locations along a single dimension.

Abstract: A method and a system for frame data to a frame sequential display device without using a frame buffer at the display device and while still maintaining the ability to use a standard interface capable of running at standard bandwidths is disclosed herein. A display system may be used to convert a multiple color frame to a plurality of single color component frames for sequential display on a display device. The display system includes a data system, a display controller, and a display device. The data system provides graphics data to the display controller. The display controller converts the graphics data into single color component frames and then transmits the single color component frames sequentially in sets of parallel data to the display device for display. The display device receives the sets of parallel data and converts the parallel data into sequential data. The sequential data is then output to a frame sequential display.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: To provide for the processing of priority data elements between a host processor and a co-processor that exchange such data elements using a queue, the host processor determines a priority of a data element received from an application. If the priority is higher than a lowest possible priority value, at least one lower priority data element within the queue may be identified and modified thereby temporarily removing it from the queue. When the priority data element is written into the queue a query packet is included that will cause the co-processor to return information regarding a last executed queued data element. Based on the returned information, the host processor can determine one or more unmodified data elements (uniquely corresponding to the one or more modified queued data elements) to be written into the queue in accordance with a sequence of the previously modified queued data elements.

Abstract: A technique for recording information in a battery operated device is provided such that quality level of the recorded information may be changed “on the fly.” In one embodiment, while persistently recording information at a first quality level, the battery operated device may, in response to an input a desire or need to change recording quality level, thereafter persistently record the information at a second quality level different from the first quality level, without interrupting the continuity of the recording session. In a presently preferred embodiment, the information being recorded may comprise video information or audio information. Subsequent inputs indicating the need to change recording quality level yet again may also be received thereby causing the battery operated device to persistently record the information at yet another quality level, which quality level may be the same as the first quality level.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: A differential signal comparator includes an input circuit operative to provide an absolute input current difference value that is associated with the absolute difference of differential input signal levels, and a reference circuit operative to provide an absolute reference current difference value that is associated with the absolute difference of the reference signal levels. Current comparison of the absolute input current difference value with the absolute reference current difference value identify whether an input differential signal is bigger than the reference noise level and should be processed, or an input differential signal is smaller than the reference noise level and should not be processed.

Abstract: A field sequence detector determines the field sequence of a series of fields of video by assessing the vertical frequency content of hypothetical de-interlaced images. Hypothetical images are formed from a currently processed field and an adjacent (e.g. previous or next) field. If the vertical frequency content is relatively high (e.g. above ½ the Nyquist frequency for the image), the hypothetical image is assessed to be formed of improperly interlaced fields, belonging to different frames. If the frequency content is relatively low, the hypothetical image is assessed to be properly assembled from fields of the same frame. The field sequence in the series of fields may be detected from the assessed frequency content for several of said series of fields. Known field sequence, such as 3:2 pull-down, 2:2 pull down, and more generally m:n:l:k pull-down sequences.

Abstract: A method and apparatus for performing multisampling-based antialiasing in a system that includes first and second graphics processing unit (GPUs) that reduces the amount of data transferred between the GPUs and improves the efficiency with which such data is transferred. The first GPU renders a first version of a frame using a first multisampling pattern and the second GPU renders a second version of a frame in the second GPU using a second multisampling pattern. The second GPU identifies non-edge pixels in the second version of the frame. The pixels in the first version of the frame are then combined with only those pixels in the second version of the frame that have not been identified as non-edge pixels to generate a combined frame.

Abstract: A data port operates to support symmetric PCI Express-type data transfers when in a first mode of operation. When in a second mode of operation, at least a portion of the data port connections are used to support an asymmetric PCI Express-type data transfer. The asymmetric data transfer is accommodated by supporting, with respect to the asymmetric data port, partial data lanes, thereby reducing the number of data channels implemented in a direction of the lower data rate transfer.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.

Abstract: A de-interlacer includes recursive motion history map generating circuitry operative to determine a motion value associated with one or more pixels in interlaced fields based on pixel intensity information from at least two neighboring same polarity fields. The recursive motion history map generating circuitry generates a motion history map containing recursively generated motion history values for use in de-interlacing interlaced fields wherein the recursively generated motion history values are based, at least in part, on a decay function.

Abstract: A power management control circuit and method thereof includes a power register that contains a number of request tokens for at least one power consumption module. The number of request tokens represents a power adjust level of the at least one power consumption module. The power management control circuit and method thereof further includes a power controller coupled to the power register, wherein the power controller determines whether to adjust the power consumption module based on a comparison of a number of system tokens with the number of request tokens for the power consumption module. The power management control circuit and the method thereof further includes a token generator coupled to the power controller. The token generator generates the predetermined number of system tokens and a token valid signal for clearing an up token register and a down token register for each predetermined time interval.

Abstract: A software or hardware test system and method repeatedly obtains testing status of a plurality of test units in a group while the test units are testing hardware or software being executed on the test units. The system and method provides for display of the current testing status of the plurality of units of the group while the plurality of test units is performing software testing. In another embodiment, a test system and method compiles heuristic data for a plurality of test units that are assigned to one or more groups of test units. The heuristic data may include, for example, data representing a frequency of use on a per-test unit basis over a period of time, and other heuristic data. The test system and method evaluates job queue sizes on a per-group basis to determine whether there are under-utilized test units in the group and determines on a per-group of test unit basis whether a first group allows for dynamic reassignment of a test unit in the group based on at least the compiled heuristic data.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: The present disclosure relates to a thermal management apparatus used to manage temperature of components mounted to a circuit substrate, such as electronic or optical components. The apparatus includes a heat dissipation structure that includes at least one protrusion extending from a surface of the heat dissipation structure. A carrier structure is also included and engages with the heat dissipation structure. The carrier structure includes an aperture that receives the at least one protrusion. Additionally, the apparatus includes at least one biasing structure that is configured to allow movement of the heat dissipation structure relative to the carrier structure and provides a biasing force tending to move the heat dissipation structure and carrier structure together.