Abstract: A method for refining and casting metals and metal alloys includes melting and refining a metallic material and then casting the refined molten material by a nucleated casting technique. The refined molten material is provided to the atomizing nozzle of the nucleated casting apparatus through a transfer apparatus adapted to maintain the purity of the molten refined material. An apparatus including a melting and refining apparatus, a transfer apparatus, and a nucleated casting apparatus, in serial fluid communication, also is disclosed.

Abstract: A thermal management device for a circuit substrate having at least a first heat generating component and at least a second heat generating component, the thermal management device includes a first thermal spreader and a second thermal spreader. The second thermal spreader is mountable to the circuit substrate to thermally couple with the second heat generating component. Additionally, the second thermal spreader is adapted to couple to the first thermal spreader to thermally couple the first thermal spreader to the first heat generating component when the second thermal spreader is mounted to the circuit substrate. The thermal management device also includes a bias device that is coupled to the first thermal spreader and the second thermal spreader and is adapted to maintain the thermal coupling between the first thermal spreader and the first heat generating component when the second thermal spreader is mounted to the circuit substrate.

Abstract: The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation station such that the arbiter retrieves a first command thread of the plurality of command threads stored therein such that the arbiter receives the command thread and thereupon provides the command thread to a command processing engine. The system and method further includes the command processing engine coupled to receive the first command thread from the arbiter such that the command processor may perform at least one processing command from the command thread. Whereupon, a command processing engine provides the first command thread back to the associated reservation station.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: An integrated differential receiver includes a single gate oxide differential receiver and an associated switchable voltage supply circuit. The integrated differential receiver determines the desired receiver supply voltage and selects a supply voltage for the single gate oxide differential receiver. When a lower supply voltage is determined as the desired supply voltage, the integrated differential receiver automatically provides a supply voltage to the single gate oxide differential receiver with a voltage higher than the I/O pad supply voltage and higher than the maximum input signal voltage to increase the speed of operation for the differential receiver. The switchable voltage supply circuit is operatively responsive to a control signal which indicates the desired supply voltage for the I/O pad. In one embodiment, both the single gate oxide differential receiver and the switchable voltage supply circuit are single gate oxide circuits.

Abstract: To receive new services including audio or video content for presentation by a cable-compatible digital television or other digital audio/video receiver, a module may be connected to the HOST-POD interface of the digital television. The module has a receiver for receiving audio or video content in a first compression format, a transcoder for converting said audio or video content from the first compression format into a second, different compression format, and a controller for transmitting the audio or visual content in the second compression format to the digital television over a HOST-POD interface. By using such a module, front-end components of the digital television may be bypassed while back-end components may be utilized to decompress and present the content. The module may be a PC card or smart card for example.

Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.

Abstract: A multiphase clock generating circuit includes a multiphase clock generator that produces a plurality of multiphase output signals at a first frequency and a multiphase divider with delayed reset control. The multiphase divider with delayed reset control is operatively coupled to receive the plurality of multiphase output signals at the first frequency and further operative to produce a plurality of multiphase output signals at a second frequency based on reset control information. As a result, an interface can be supplied with and switch between multiphase clock at different frequencies within a short amount of time with reduced power consumption and circuit area.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.

Abstract: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.

Abstract: A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction.

Abstract: In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types The ordered requests are then delivered to memory Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: A frame buffer is divided into tiles of, for example, 32 by 32 pixels. Triangles (and portions thereof) that are within a given tile are rasterized one triangle at a time into the tile location. This process repeats for each tile in the image frame. A sorting circuit generates control bits representing a vertical order of the vertices of a current triangle. A series of multiplexers vertically sorts the vertices bases on these control bits. A region calculation circuit generates region bits representing a location each of the vertices with respect to the current tile. A trivial discard of the triangle data occurs if the region bits indicate that the entire triangle lies outside of the tile. Subsequently, an initial rasterization starting point is estimated based on the region bits to lower the time needed for the rasterizer to find the first pixel of the current triangle to be assigned values.

Abstract: According to the present disclosure, a transmitter for transmitting control characters to a display device over an interface includes a transmitter portion configured to transmit a control character having a plurality of bit values to the display device. The transmitter also includes logic configured to determine values of the bits in the control character and construct a corresponding plurality of rebalancing control characters based on the determination of the values of the plurality of bits in the control character to have bit values selected such that the combination of the control character and rebalancing control character is DC balanced. As such, the transmitter provides DC balance correction to non-DC balanced control characters in such a way as to allow DVI and HDMI to operate properly on an AC-coupled connection.

Abstract: A multi-die module is electrically connected to both an unpackaged die and a packaged die as disclosed herein. The multi-die module has a footprint that is the same as conventional multi-die packages, which do not include packaged die, thereby allowing the multi-die module to be interchangeable with conventional multi-die packages. In one embodiment, the unpackaged die is a graphics processor, and the packaged die is a standard memory that has been burned in, functionally tested, and speed rated.

Abstract: A method and apparatus provides context switching of logic in an integrated circuit using one or more test scan circuits that use test data during a test mode of operation of the integrated circuit to store and/or restore non-test data during normal operation of the integrated circuit. The integrated circuit includes context control logic operative to control the test scan circuit to at least one of: store and restore context state information contained in functional storage elements in response to detection of a request for a change in context during normal operation of the integrated circuit.

Abstract: A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of overlapping discrete monotonic transfer function segments, wherein at least one point of non-monotonicity occurs among one or more of the plurality of overlapping discrete monotonic transfer function segments, and a gain segment translator circuit operative to translate a monotonic gain value to a segment code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

Abstract: A method and apparatus for enlarging an output display includes a message hook application capable of receiving a magnification event indicator, wherein the magnification event indicator includes a magnification factor. The method and apparatus further includes a character generator coupled to the message hook application wherein the character generator receives a text call from the message hook application. The character generator thereupon generates a magnified character set including a plurality of characters enlarged by the magnification factor. A display driver is coupled to the message hook application and the character generator, wherein the display driver receives the character set at the magnified font size and caches the character set. A direct draw surface is coupled to the display driver such that the direct draw surface receive one or more of the characters enlarged by the magnification factor.