Abstract: A portable device is provided. The portable device includes a first graphics controller to generate a first rendered graphics data to be displayed on an integrated display, the first graphics controller including a first output coupled to the integrated display. The portable device further includes a second graphics controller to generate a second rendered graphics data and a display interface to format the second rendered graphics data for output to a first remote display, where the display interface includes a first input coupled to an output of the second graphics controller.

Abstract: Original RF carriers are recovered for first and second channels in a diversity receiver and used to de-rotate (demodulate) each of the first and second received signals. The pilot loop filters of each channel are cross coupled to create a joint pilot loop between both channels. The channel with the stronger signal provides a dominant influence on the frequency of the synthesized recovered RF carrier in the channel with the weaker signal. The phase locked pilot loops in both channels will tend to be frequency locked to the frequency of the stronger signal, leaving the respective phase locked pilot loops to make an individual phase adjustment for each channel.

Abstract: A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus.

Abstract: A computer has a multi-stage execution pipeline and an instruction decoder.

Abstract: A method for determining the appearance of a pixel includes receiving fragment data for a pixel to be rendered; storing the fragment data; and determining an appearance value for the pixel based on the stored fragment data, wherein a portion of the stored fragment data is dropped when the number of fragment data per pixel exceeds a threshold value enabling large savings in memory footprint without impacting perceivably on the image quality. A graphics processor includes a rasterizer operative to generate fragment data for a pixel to be rendered in response to primitive information; and a render back end circuit, coupled to the rasterizer, operative to determine a pixel appearance value based on the fragment data by dropping the fragment data having the least effect on pixel appearance.

Abstract: A multi-die module is electrically connected to both an unpackaged die and a packaged die as disclosed herein. The multi-die module has a footprint that is the same as conventional multi-die packages, which do not include packaged die, thereby allowing the multi-die module to be interchangeable with conventional multi-die packages. In one embodiment, the unpackaged die is a graphics processor, and the packaged die is a standard memory that has been burned in, functionally tested, and speed rated.

Abstract: A system for generating and applying alpha values is discussed. Different sets of alpha values are generated and stored for each color component of a set of image data associated with a foreground object. A graphics-processing engine processes the foreground object with respect to a background object to be displayed in the same location. Red components of the foreground object are blended with red components of the background object using red-specific alpha values. Blue components of the foreground object are blended with blue components of the background object using blue-specific alpha values and green components of the foreground object are blended with green components of the background object using green-specific alpha values.

Abstract: A method and apparatus from removing image compression artifacts includes comparing a center pixel value with a perimeter pixel value to generate a compare pixel value. The compare pixel value is compared with a threshold value such that when the compare pixel value is below a threshold value, a count value is incremented and an accumulation value is accumulated. The method and apparatus includes repeating the comparison of perimeter pixel values with the center pixel values. The method and apparatus further includes if the count value has been incremented, generating an output center pixel value based on the quotient of the accumulation value divided by the count value as the center pixel value.

Abstract: A method and apparatus for basic input/output system (BIOS) loading includes a graphics processor performing a startup operation. The method and apparatus further includes this central processing unit (CPU) having a cache memory disposed therein. The method and apparatus provides for the graphic processor writing data to the cache memory prior to the execution of the startup operations such that the graphics processor may effectively and efficiently use the expanded memory resources of the cache memory prior to the CPU allocating and utilizing the CPU-specific resources. As such, the method and apparatus allows for improved BIOS loading by allowing for a greater degree of flexibility with an improved amount of available memory resources.

Abstract: A high density interconnection device includes a high density connector block having a plurality of jacks disposed on the outer surface for common interconnected to a high density connector. A recessed portion formed on the first side surface defines a first multi-faceted surface having a plurality of angularly disposed first surface elements. A projecting portion formed on the second side surface defines a second multi-faceted surface having a plurality of angularly disposed second surface elements. In another embodiment, one group of jacks are defined in a first plane, and another group of jacks are defined in a second plane. The first and second planes are substantially parallel such that the first and second groups of jacks are offset.

Abstract: A method and apparatus for SSA dead code elimination includes examining a first instruction off a worklist, wherein the first instruction includes previous link and a write mask and the first instruction is an SSA instruction. The method and apparatus further includes examining at least one second instruction of the machine code, wherein the at least one second instructions are sources of the first instruction and the at least one second instructions are SSA instruction. In the method and apparatus, each of the at least one second instructions include a previous link and a write mask. The method and apparatus further includes determining if any elements within a particular field are live for the at least one second instruction. If no the elements are live, the method and apparatus provides for deleting the first instruction from the machine code as it is determined that this instruction is extraneous, dead code.

Abstract: A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.

Abstract: A drive controller monitors a dynamic condition to determine when a transmission line impedance is to vary. In one embodiment, a specific bit pattern associated with a set of data lines can be monitored by the drive controller. Based upon the dynamic condition, the drive controller will determine whether or not the drive strengths of the output drivers associated with the data lines are to be adjusted. The variance in line is compensated for by independently increasing or decreasing drive strengths at the individual output nodes of the drivers.

Abstract: The present invention includes a method and apparatus for graphics processing in a handheld device including a transform engine capable of receiving vertex information. The transform engine generates a plurality of vertices from the vertex information, wherein each of the vertices includes a corresponding bin identifier. The method and apparatus further includes view frame factors defining a clipping region such that when any of the plurality of vertices is within the clipping region, a clip identifier is generated for that vertex using the corresponding bin identifier. A vertex shader coupled to a clipping module, wherein the clipping module generates supplemental vertices and the vertex shader receives the supplemental vertices therefrom. The vertex shader combines the supplemental vertices with the bin identifiers and are provided to a vertex buffer.

Abstract: A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further includes a first memory device storing a plurality of instructions wherein each of the plurality of instructions includes a plurality of extra bits. The processor is operative to execute the instructions based on the extra bits and in conjunction with a context bit. The method and apparatus further includes a second memory device, such as a general purpose register operably coupled to the processor, the second memory device receiving an incrementing counter instruction upon the execution of one of the plurality of instructions. As such, the method and apparatus allows for nested control flow through a single context bit in conjunction with instructions having a plurality of extra bits.

Abstract: A reference signal input of a delay locked loop is connected to receive a reference clock. The delay locked loop provides a drive clock that drives a clock distribution tree. One of the endpoints of the clock distribution tree is connected to a feedback reference of the delay locked loop. By using one the endpoints as a feedback loop to the delay locked loop the signal received at components attached to the endpoints of the distribution tree can be synchronized to the reference input received at the delay locked loop.

Abstract: A method and apparatus for constructing an executable program, such as drivers in memory, obtains system configuration parameters and dynamically constructs driver code bundles from a set of code modules obtained from a library, based on the actual system configuration parameters. The set of code modules includes code modules associated with a plurality of system configuration parameters. One example of the system configuration parameter include static system configuration parameters such as in the case of a computer, a CPU type, clock speed and system memory size. Other actual system configuration parameters include dynamic configuration parameters which can be changed by the user. One example of a dynamic configuration parameter may be, for example, pixel depth and display screen resolution. After obtaining optimal system configuration depending upon a system's setting or configurations, dedicated code modules are used and stored in system memory or other suitable memory.

Abstract: A system and methods are provided for a controlled transfer of a portion of a data stream between a digital storage media and a corresponding stream decoder. A data stream stored in digital storage media is accessed through an application. A FIFO is used to provide a buffer to the stream decoder. The application monitors the FIFO to determine when to send data related to the data stream from the digital storage media. The data is transferred to the buffer and passed to the stream decoder. A counter is used for dictating a period of time between sending segments of the data stored in the FIFO to the stream decoder. The rate of transfer to the stream decoder is adjusted through the counter to match a desired bit-rate associated with the data stream.

Abstract: The present invention provides for a method and apparatus for multimedia display in a mobile device including a multimedia processor capable of generating a multimedia display output. The method and apparatus further includes a multimedia display buffer and a camera interface coupled to the multimedia processor, wherein the multimedia processor is capable of receiving a captured image from a camera. The method and apparatus further includes a multimedia device interface that is capable of receiving an encoded multimedia display command encoded in a multimedia device interface command protocol. Thereupon, the encoded multimedia display command is generated, such that the multi-media processor can generate the multimedia display output and provide the multimedia display output to the display device.

Abstract: A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.