Abstract: A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.

Abstract: An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.

Abstract: A system and method for converting text data having a Teletext format to text data having an Electronics Industries Associations-608 (EIA-608) format are illustrated herein. A video stream with embedded text data having a Teletext format is received by a dual mode text processing system. The dual mode text processing system, in one embodiment, extracts the text data and filters the text data to identify a desired portion using an identifier, such as a page identifier or number. The desired portion (or a copy thereof), once identified, is sent to a line break parser. The line break parser, in one embodiment, eliminates some or all of any unnecessary or unintended line breaks, as well as some or all of any extra space characters, to generate a character stream. The character stream, in one embodiment, is then converted into a EIA-608 format by a line convertor, wherein the character stream is parsed into one or more subtitle lines with a maximum character length.

Abstract: An audio/video separator provides a high-performance and cost-effective solution to analog TV reception with only one A/D converter and a minimum of analog IF components. The apparatus may operate on a digitized TV signal and, when integrated with a digital video processor, process video signals while separating audio signals. The resultant audio and video signals may be considered to have excellent signal quality due to highly optimized demodulation architecture and digital signal processing techniques on both audio and video data paths.

Abstract: A dynamic component to input signal mapping system is disclosed that receives different types of input signals applied to a number of components and provides resultant output signals. The system includes input ports receiving the input signals, output ports providing the output signals, and a number of components processing the input signals, each of the components having at least one input and one output. The system includes a test signal source coupled to the components. Additionally, a signal analyzer coupled to an output of components analyzes response signals output from the components in response to test signals. The system is operative to map at least one component to receive at least one input signal based on the analyzed response. The system allows components on a semiconductor chip to be dynamically reconfigured for optimal processing of different types of signals, such as video and audio signals.

Abstract: A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requirements. Power is conserved by reducing clock speeds from unnecessarily high rates to a rate that can satisfy current display mode settings and other graphics processing demands.

Abstract: A method and apparatus for enlarging an output display includes a message hook application capable of receiving a magnification event indicator, wherein the magnification event indicator includes a magnification factor. The method and apparatus further includes a character generator coupled to the message hook application wherein the character generator receives a text call from the message hook application. The character generator thereupon generates a magnified character set including a plurality of characters enlarged by the magnification factor. A display driver is coupled to the message hook application and the character generator, wherein the display driver receives the character set at the magnified font size and caches the character set. A direct draw surface is coupled to the display driver such that the direct draw surface receive one or more of the characters enlarged by the magnification factor.

Abstract: A method and apparatus for processing real time command information includes a real time event engine that monitors event signals. A real time event detector within the real time event engine detects when the real time event occurs. Thereupon, real time event commands within a real time event command buffer are fetched and consumed by the command processor in response to the occurrence of the real time event. The real time event detector contains a plurality of control registers, which contain an event selector register, a real time command buffer point register, and a real time command buffer length register. A driver may program the registers, whereupon a singe real time event detector may be used in conjunction with a plurality of real time event command buffers.

Abstract: A multi-position electrical connector for a robotic tool changer includes a bracket mountable to a robotic tool changer master or tool module, a coupling interface in a fixed position with respect to the bracket, and a cable interface moveable to a plurality of positions with respect to the bracket. Both the coupling interface and the cable interface include a plurality of electrical contacts, which are electrically connected. In one embodiment, the cable interface is disposed at substantially 90 degrees to the coupling interface, and is rotatable about an axis of the coupling interface. The cable interface may be fixed in one of a plurality of positions around the coupling interface. In one embodiment, a selected position is fixed by mating a retention member on one of the cable interface and the bracket, with a recess on the other of the cable interface and the bracket.

Abstract: In a graphics processing circuit, up to N sets of state data are stored in a buffer such that a total length of the N sets of state data does not exceed the total length of the buffer. When a length of additional state data would exceed a length of available space in the buffer, storage of the additional set of state data in the buffer is delayed until at least M of the N sets of state data are no longer being used to process graphics primitives, wherein M is less than or equal to N. The buffer is preferably implemented as a ring buffer, thereby minimizing the impact of state data updates. To further prevent corruption of state data, additional sets of state data are prohibited from being added to the buffer if a maximum number of allowed states is already stored in the buffer.

Abstract: A method and apparatus for hierarchical Z buffering stenciling includes comparing an input tile Z value range with a hierarchical Z value range and a stencil code. The method and apparatus also updates the hierarchical Z value range and stencil code in response the comparison and determines whether to render a plurality of pixels within the input tile based on the comparison of the input tile Z value range with the hierarchical Z value range and stencil code. In determining whether to render the tile, a stencil test and a hierarchical Z value test is performed. If one of the test fails, the tile is killed as it is determined that the pixels are not visible in the graphical output. If the stencil test passes and the hierarchical Z test passes, the pixels within the tile are rendered, as it is determined that the pixels may be visible.

Abstract: A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generator produces graphics engine clock control information and memory clock control information with respect to each other, such that a relative difference between the graphics engine activity data and the memory activity data is within balance threshold data. Accordingly, the variable clock control information generator adapts to the varying levels of graphics engine activity and memory activity and adjusts the frequency of the graphics engine clock signal and the frequency of the memory clock signal to achieve a balanced relative activity level.

Abstract: A method and apparatus for object-based visibility culling includes receiving a plurality of draw packets, such as pixels or vertices. The method and apparatus further includes comparing each of the plurality of draw packets to a bounding volume object, wherein the bounding volume object may be a low resolution geometric representation of a specific object. Whereupon, for each of the plurality of draw packets, if the draw packet is deemed potentially visible, setting a visibility query identifier and rendering the draw packets having the set visibility query identifier.

Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.

Abstract: A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the input signal. The method and apparatus further includes a comparator coupled to receive an input strength indicator signal from the receiver and operative to generate a comparative strength signal based on the comparison of the input signal strength indicator signal and a reference strength signal. Furthermore, the method and apparatus includes a tuner coupled to the clock counter so the tuner receives the time value from the counter, and coupled to the comparator to receive the comparative strength signal from the comparator, whereupon the tuner then generates a tuning signal utilized for an iterative tuning process to fine tune a memory interface.

Abstract: A method and apparatus for superword register value numbering includes hashing an operation code and the value numbers of a plurality of sources to generate a first hash value. The method and apparatus further includes retrieving an operation value number from the first hash table based on the first hash value. The method and apparatus further includes generating a result value number based on a previous bit hash value and the operation value number. The result value number is a combination of the operation value numbers for each component having a live indicator and a previous value numbers for the components without the live indicator. Thereupon, the method and apparatus includes searching a second hash table using the result value number. As such, the method and apparatus provides using two separate hash tables for value numbering with superword instructions.

Abstract: A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to the computer's physical address space. Profile circuitry is cooperatively interconnected with the instruction pipeline and configured to detect, without compiler assistance for execution profiling, occurrence of profilable events occurring in the instruction pipeline, and is cooperatively interconnected with the memory access unit to record profile information describing physical memory addresses referenced during an execution interval of the program.

Abstract: A method and apparatus for processing non-planar video graphics primitives is presented. Vertex parameters corresponding to vertices of a video graphics primitive are received, where the video graphics primitive is a non-planar, or higher-order, video graphics primitive. A cubic Bezier control mesh is calculated using the vertex parameters provided for the non-planar video graphics primitive. Two techniques for calculating control points included in the cubic Bezier control mesh along the edges of the non-planar video graphics primitive are described. The central control point is determined based on the average of a set of reflected vertices, where each of the reflected vertices is a vertex of the non-planar video graphics primitive reflected through a line defined by a pair of control points corresponding to the vertex.

Abstract: A method and apparatus for pixel conversion using multiple buffers includes receiving a position value including a horizontal value and a vertical value. The method and apparatus further includes receiving a byte per pixel value and a pixels per group. The method and apparatus further includes determining a pitch value for each of the multiple buffers and determining an offset value for each of the multiple buffers. The method and apparatus further includes assigning each of the multiple buffers to varying buffer locations within a frame buffer based on the position value, the byte per pixel value and the pixels per group value such that a first and second converted pixel values may be equivalent to a first and second corresponding assigned buffer location.

Abstract: An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected object data of the digital image and image object library data associated with image descriptor library data. An automated library user interface presents selectable matched object descriptor data associated with the image descriptor library data when a recognition match occurs between the selected object data of the digital image and the image descriptor library data. In response, the automated library user interface provides user feedback data to confirm that the image descriptor library data corresponds with the selected object data of the digital image, or entered descriptor data if no match or an incorrect match occurs, to create library descriptor associated image data.