Abstract: A method and apparatus for generating a multimedia document that includes video image samples and associated audio is accomplished by decoding video signals into decoded video representations, sampling the decoded video representations at a rate below the motion video frame rate, and storing the video samples as a video document. For example, a JPEG document. In addition to creating video documents, the present method and apparatus also digitizes received audio signals and stores the digitized audio as an audio document. For example, as an AIFF (audio interchange file format audio format audio document, a WAV (which is used with Windows™) audio document, or a RealAudio™ (which is the Internet standard for delivering continuous audio) audio document. Once the video document(s) and audio document(s) are created, they are mapped together and stored as a multimedia document, which may be a hypertext document, such as an HTML document.

Abstract: A method and apparatus for storing data for a plurality of data blocks in a compressed format in memory is presented where the compression scheme used for compressing the data blocks may vary. For each data block included in the plurality of data blocks, the data block is compressed using a compression scheme that is included in a set of predetermined compression schemes. The resulting compressed data set is of a size included in a set of predetermined sizes that correspond to the particular compression scheme utilized. The compressed data set for each block is then stored in a compressed data set memory, where the compressed data sets are stored in groups. A descriptor data set corresponding to each group is then stored in a descriptor memory, where the descriptor data set includes an encoded compression descriptor for each data block included in the group. The data descriptor set also stores a base address that corresponds to a starting location for that group in the compressed data set memory.

Abstract: A method and apparatus for generating a specific computer hardware component exception handler and emulating memory accesses to such a hardware component include processing steps that begin by determining whether an address of a CPU instruction is within the address space of the computer hardware component. When the address is within the address space of the computer hardware component, the address and data size are saved in emulation registers. The processing then continues by entering a software exception handler to process the memory access requests directed to the computer hardware component based on the data size. The processing within the software exception handler begins by reading from a plurality of computer hardware component registers to obtain a register setting. The processing then continues by generating a specific computer hardware component function based on the register settings. The processing then continues by storing the specific computer hardware component function in cache memory.

Abstract: In one embodiment of the present invention, a 10-bit encoded video word is received and stored as two five-bit representations. One of the stored five-bit representations is selected by a multiplexor and provided to a parallel-to-serial converter. The parallel-to-serial converter receives control signals from a multiphase clock. Specifically, the multiphase clock provides a five-phase multi-phased clocks in order to control the parallel-to-serial converter. The serial-to-parallel converter provides a 10-bit serial representation of the 10-bit encoded input.

Abstract: A circuit is provided for performing a high-precision bilinear interpolation operation. The circuit includes a first interpolation operator for interpolating two operands representing a pair of texels using a weight high component of a weighting value. The first interpolation operator outputs a first result. A second interpolation operator interpolates the two operands representing the pair of texels using a weight low component of the weighting value. The second interpolation operator outputs a second result. A combination operator, coupled to the first and second interpolation operators, combines the first and second results to form a value of higher precision than that yielded by typical circuit implementations for bilinear interpolation operation.

Abstract: An apparatus and associated method for manipulating an electrode comprising a stub, an electrode, and a yoke. The stub is affixed to and protrudes from the electrode, and has a first opening. The yoke is sized to receive at least a portion of the stub, and has a second opening positioned for alignment with the first opening of the stub and receipt of a locking member extending through the first opening and the second opening. The apparatus may include a current conducting tube. The elongated yoke may extend around at least a portion of the stub to be removably pinned thereto. The current conducting tube may extend around the elongated yoke to be in electrical contact with the stub.

Abstract: A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle.

Abstract: A cutting tool insert comprises a hard metal substrate having at least two wear-resistant coatings including an exterior ceramic coating and a coating under the ceramic coating being a metal carbonitride having a nitrogen to carbon atomic ratio between 0.7 and 0.95 which causes the metal carbonitride to form projections into the ceramic coating improving adherence and crater resistance of the ceramic coating. Also disclosed is a cutting tool insert including a hard substrate and at least first and second coatings on at least a portion of said substrate. The first coating is of at least about 2 microns, is in contact with the substrate, and includes at least one of a metal carbide, a metal nitride, and a metal carbonitride of a metal selected from the group consisting of zirconium and hafnium. The second coating may include at least one of a metal carbide, a metal nitride, and a metal oxide of a metal selected from groups IIIA, IVB, VB, and VIB of the periodic table.

Abstract: A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.

Abstract: A digital-to-analog converter includes a number of current steering cells. In each current steering cell, a current source is biased by a differential amplifier to provide a high output impedance. The high output impedance in the current steering cell allows the digital-to-analog converter to operate under low supply voltage conditions.

Abstract: A method and apparatus for determining and utilizing Z values of fragments in an anti-aliasing video graphics system is described. This method and apparatus are accomplished by sampling the fragment to produce a plurality of samples where a valid sample indicate coverage of a pixel by the fragment at a portion of the pixel corresponding to the valid sample. The Z value of a front-most valid sample of the plurality of samples is then determined. This Z value is preferably determined by determining the Z value at a reference point within the pixel and then ranking the various samples based on their positions and the slopes of the Z value in the horizontal and vertical directions with respect to the reference point. The highest ranked sample that is a valid sample is then selected, and the Z value for that sample is calculated based on the Z value at the reference point, the position of the selected sample with respect to the reference point, and the slopes.

Abstract: An analog to digital converter having a group of subrange analysis blocks and reference voltage and offset voltage selection blocks. Each subrange analyses block produces an output representative of a range of bits in a digital output of the analog digital converter. The reference voltage and offset voltage selection blocks enable the operating conditions for the next subrange analysis block to be optimized for both linearity and operating speed.

Abstract: Improved television tuning circuits are disclosed. An example tuning circuit includes a fraction-N frequency synthesizer facilitating fine tuning. This tuning circuit may be formed using relatively few independent oscillators. The tuning circuit lends itself to the formation of an tuning circuit on an integrated circuit substrate. As well, this tuning circuit may be used to form a dual tuner tuning circuit integrated on a single integrated circuit substrate.

Abstract: A method and apparatus for interfacing memory with a bus in a computer system includes processing that begins by receiving a transaction from the bus. The transaction may be a read transaction and/or a write transaction. Upon receiving the transaction, the process continues by validating the received transaction and, when valid, acknowledges its receipt. The processing then continues by storing the physical address, which was included in the received transaction, and the corresponding command in an address/control buffer. The processing continues by retrieving the physical address from the address/control buffer when the transaction is to be processed. The determination of when the transaction is to be processed is based on an ordering within the address/control buffer. The processing then continues by performing the transaction utilizing a first or second memory path based on the physical address, such that a first or second memory is accessed.

Abstract: A multiplier carry bit compression apparatus and method for a multiplier using Wallace tree addition structures uses a plurality of early and late carry bit compression operations for each level of the Wallace tree addition structure. For each level in a Wallace tree addition structure, each early carry bit compression operation compresses early compression bits prior to each corresponding late carry bit compression operation that compresses late carry bits.

Abstract: A memory access device is presented that synchronously transfers data between contiguous memory locations and a set of potentially non-contiguous registers, via a single load, or move, command. An address generator generates a series of contiguous memory addresses and a corresponding set of potentially non-contiguous register addresses in dependence upon the contents of a variable format command. In this manner, the data transfer efficiencies achievable by a block transfer of contiguous data elements can be achieved while simultaneously transferring the data to and from non-contiguous register locations. The memory access device may also include a data converter which optionally converts the data elements contained in memory to and from another form, such as from integer to floating point, during the data transfer process.

Abstract: A dual-cache pixel processing circuit that allows one cache to be flushed while the other receives subsequent pixel fragments is presented. The system includes a first fragment cache and a first set of state registers where the first set of state registers stores state variables for drawing operations corresponding to fragments stored in the first fragment cache. The system also includes a second fragment cache and a second set of state registers where the second set of state registers stores state variables for drawing operations corresponding to fragments stored in the second fragment cache. The system further includes a render backend block that is operably coupled to the first and second fragment caches and to a frame buffer that stores current pixel information for a plurality of pixels in a display frame.

Abstract: A method and apparatus for interfacing a processor with a bus includes processing that begins by storing transactions initiated by the processor into a buffer. The processing then continues by selecting one of the transactions stored in the buffer and placing the selected transaction on the bus. The processing continues by monitoring progress of fulfillment of each transaction in the buffer and flagging a transaction when it has been successfully completed. The processing also includes processing at least two related transactions prior to selecting one of the transactions from the buffer where, if transactions can be processed locally, they do not need to be transported on the bus. In addition, the processing includes monitoring the bus for related transactions initiated by another processor such that these transactions can be more efficiently processed. The related transaction on the bus would correspond to a transaction queued in the buffer.

Abstract: A method and apparatus for antialiasing in a video graphics system is accomplished by determining if a pixel sample set, which results from oversampling, can be reduced to a compressed sample set, where the compressed sample set contains information describing a corresponding pixel. When the pixel sample set can be reduced to a compressed sample set, the compressed sample set is stored in a frame buffer at a location corresponding to the particular pixel that the sample set describes. When the pixel sample set cannot be reduced to a compressed sample set, a pointer is stored at the frame buffer location corresponding to the particular pixel. The pointer points to a selected address in a sample memory at which the complete sample set for the pixel is stored.

Abstract: A text data extraction system analyzes one or more interleaved video data streams and parses the stream(s) to extract text data from text data packets. In addition, presentation time data is extracted to facilitate independent use of the text data from corresponding video data. Extracted time coded text data is stored so that the presentation time data can be used to link the extracted text data back to the corresponding video data to facilitate for example: annotation of a movie, text searching of closed caption text, printing transcripts of closed caption text, controlling video playback, such as the order in which scenes are played back, and any other suitable navigation or manipulation of video images or text data.