Abstract: A method and apparatus for storing sequential data words associated with a block of data in a non-linear manner within the data block is taught such that any row or column associated with the data block may be accessed using a burst access. A row, or column of data accessed by a burst frees up instruction bandwidth of a video controller. In particular, it is assured that each row and column of data associated with the data block has at least one sequential pair of data words associated with it. By assuring at least one sequential pair of data words, it is possible to issue a burst request for a minimum of two words of data with each row access, or column access of the video controller.

Abstract: A method and apparatus for multipass pixel processing is presented. A command stream that includes a plurality of drawing commands is received where multipass drawing commands included in the stream include a number of sets of state information and one or more graphics primitives. For a multipass pixel processing operation, the graphics pipeline that performs the pixel processing is first configured using a first set of state information included in the sets of state information for the multipass operation. Once the graphics pipeline has been configured, at least a portion of the processing to be performed for the drawing command is performed using the graphics pipeline as configured by this first set of state information. The resultant data produced through this processing is stored as intermediate data. This may be referred to as the first pass in the multipass operation. The graphics pipeline is then reconfigured using a subsequent set of state information corresponding to the multipass drawing command.

Abstract: A voltage supply discriminator circuit senses multiple logic voltage supply levels and produces a plurality of control signals to select either or both of an output buffer circuit and/or an input buffer circuit that is coupled to a pad or pin. The discriminator circuit utilizes an input/output ring voltage supply and a reference voltage, such as a core voltage supply, to determine the appropriate circuitry to be used for the I/O pad. The appropriate circuitry is then automatically activated.

Abstract: A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials.

Abstract: In accordance with a specific embodiment of the present invention, an application for providing static images requests an overlay window. Examples of such static images include JPEG, GIF, TIFF, and bitmapped images. The overlay request is granted by system drivers. Once the overlay window has been provided an enhanced static image is provided to the image driver from a still image application. The image driver will store the static image in the overlay memory area whereby it is displayed in an enhanced mode upon the display device.

Abstract: A method and apparatus for parallel processing of pixel information within a video graphics circuit is accomplished when the video graphics circuit includes a set-up engine, an edgewalker circuit, a span processing circuit, and a plurality of pixel processing circuits. In such an embodiment, the set-up engine receives vertex information and produces object-element information therefrom. The object-element information is provided to the edgewalker circuit, which in turn produces span definition information. The span definition information identifies the starting pixel of a span and the starting pixel parameters. The span information is received by the processing circuit and converted into a plurality of pixel parameters. The plurality of pixel parameters are provided to the plurality of pixel processing circuits wherein each of the plurality of pixel processing circuits processes corresponding pixel parameters to produce pixel information in accordance with the information provided by the processing circuit.

Abstract: A method and apparatus for graphics processing that utilizes multiple graphics processors in parallel is presented. A primary graphics processor is operably coupled to a primary memory that includes a primary color buffer and a primary Z buffer. The primary processor processes a first portion of the image data for a frame, where processing the first portion stores color data in the primary color buffer and Z data in the primary Z buffer. A secondary processor is operably coupled to a secondary memory that includes a secondary color buffer and a secondary Z buffer. The secondary processor processes a second portion of the image data for the frame. The processing of the second portion of the image data results in color data being stored in the secondary color buffer and Z data being stored in the secondary Z buffer. The display signal that results in the image data for the frame being displayed is generated by a display driver included in the primary processor.

Abstract: An amorphous metal alloy strip is disclosed having a width greater than about one inch and a thickness less than about 0.003 inch, this alloy consists essentially of 77 to 80 atomic percent iron, 12 to 16 atomic percent boron and 5 to 10 atomic percent silicon with incidental impurities. The strip has a 60 cycle per second core loss of less than about 0.100 watts per pound at 12.6 kilogauss, saturation magnetization of at least 15 kilogauss, and a coercive force of less than about 0.04 oersteds. Such alloy is further characterized by increased castability and the strip produced therefrom exhibits at least singular ductility. A method of producing such optimum strip is also disclosed.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A multistream data packet transfer apparatus and method receives data for at least one stream of multistream data from multiple fragments of memory, over a bus from a first processor. The first processor stores multistream data in the fragmented memory. An interface controller, such as any suitable logic and /or software, evaluates the received data to determine which received data is usable data for a second processor. A data packer removes unusable data and packs the usable data in fixed sized units to form a data packet for the second processor. The data packer packs data received from different fragments of memory as a single packet for use by a DSP requesting the information.

Abstract: A novel pipeline processing system includes a parameter bus and a command processor. The command processor receives a command, generates a word in response to the command, and transmits the word on the parameter bus. The word includes information identifying whether the word includes state parameter data and information identifying whether the word includes immediate mode parameter data. A plurality of pipeline stages are positioned along the parameter bus. Each pipeline stage has a state register and a logic block both connected to the parameter bus. The state register receives the word and stores the state parameter data included in the word in response to the information identifying whether the word includes state parameter data. The logic block receives the word and performs a logic operation using state parameter data stored in the state register and the immediate mode parameter data included in the word in response to the information identifying whether the word includes immediate mode parameter data.

Abstract: A method and apparatus for blending a plurality of image input layers include processing that begins by converting each of a plurality of image input layers that have a color base that differs from a color base of a display into a image layer having the color base of the display, thereby producing converting image layers. The color base of the image input layers and of the output include the colorimetries of various standardized video signals, color space, and/or any other defining display characteristics of video signals that is currently standardized or maybe standardized. Further note that an image input layer corresponds to a window, a background and/or a display area of a display, where the display is capable of presenting more than one image, where the images originate from different video and/or graphics data sources (e.g., a television signal, and a computer application display).

Abstract: A method and apparatus for compression of a two dimensional video object such that the video object may subsequently be displayed as a three dimensional object is generally accomplished by a set-up engine which receives vertex parameters and generates a plurality of derivatives and Bresenham parameters, therefrom. The derivatives and Bresenham parameters are provided to an edgewalker circuit which produces, therefrom, a plurality of spans which, in turn, is converted in to a set of texel addresses by a texel address generator. A texel fetch circuit receives the set of texel addresses and uses the addresses to retrieve a set of texels, which is subsequently processed by a texel processor to produce a filtered pixel. To retrieve the set of texels, the texel fetch circuit retrieves a set of indexes based on the texel addresses and uses the set of texels to retrieve the set of texels from a codebook.

Abstract: A memory clock control system and method facilitates power reduction on a dynamic basis by detecting memory access request loading from a number of memory access devices, such as video and graphics engines. Based on the detected memory access requirements, the system and method adaptively varies a memory clock frequency in response to determining the desired memory usage at a given point in time. The memory clock is varied based on the priority of a given memory access engine, such that the clock is kept or increased to a higher rate for high priority engines such as real-time processing engines to facilitate high performance video capture.

Abstract: A circuit for shifting the number of partial product bits per column in an adder tree is provided. A partial product bit is generated having a weight 22k that has a 1 value only if one input bit of weight 2(k−1) has a 0 value while another input bit of weight 2k has a 1 value. Another more significant partial product bit of weight 2(2k+1) receives the same input bits and has a 1 value only if both of the input bits have a 1 value. In this manner, the number of partial product bits in the column of weight 22k is decreased by 1 while the number of bits is the column of weight 2(2k+1) is increased by 1. Therefore, if the column of weight 22k had the greatest number of partial product bits of all columns, and if the column of weight 2(2k+1) had at least two fewer bits than the column of weight 22k, the total maximum number of bits for all the columns is reduced by 1.

Abstract: An electrostatic discharge circuit utilizes a cascaded transistor configuration and a dual ESD protection circuit configuration. Preferably, the ESD protection circuits are made as a single gate oxide circuit. The protection circuit is effectively disabled during normal operation and allows a variable level voltage input to be applied during normal operation without damage to the cascaded transistors.

Abstract: A method and apparatus for determining a clipping distance of vertices of object-element with respect to a clipping plane include processing that begins by obtaining a clipping distance for each original vertex of an object-element with respect to the clipping plane. The processing then continues by obtaining a barycentric coordinate of the vertex of the object-element that represents of an intersection of an edge of the object-element with a previously processed clipping plane. The processing then continues by deriving a clipping distance from the vertex to the clipping plane based on the barycentric coordinate of the vertex and the clipping distance for each of the original vertices.

Abstract: In one embodiment of the present invention, a plurality of video images are displayed on a scalable window associated with a computer device. One of the first portion of the plurality of images is updated by a first tuner, a second portion of the plurality of images is updated by a second tuner. By selecting one of the plurality of images using a first method, the selected image can be viewed in full-motion-video. By selecting an image using a second selection method, the image can be viewed in full-motion-video for only a predetermined amount of time. By selecting the image in yet another selection method, a second window can be created whereby a larger image of the thumbnail image can be viewed in full-motion-video. Yet another video image can be selected in order for the audio associated with that video to be played. Images being monitored in slow motion video may be relegated to the status of a thumbnail through various selection methods.

Abstract: A multi-pass pixel processing circuit and method that allows a single set of texturing circuitry to be used for performing texture mapping operations that map multiple texture maps to a video graphics primitive is presented. The multi-pass pixel processing circuit includes a raster engine that is operably coupled to receive primitive parameters corresponding to video graphics primitives. For each portion of a selected primitive, the raster engine performs a first pass of texture map coordinate generation. During the first pass, the raster engine generates a first set of texture map coordinates corresponding to a first texture map for each pixel in the portion of the selected video graphics primitive. A coordinate combination block that is operably coupled to the raster engine provides the first set of texture map coordinates for each pixel to a memory that stores the first texture map to retrieve texture data corresponding to the first texture map for each pixel.

Abstract: A method and apparatus for supporting accumulation buffering in a video graphics system is presented. An accumulation buffer is included in the system, and the accumulation buffer stores an accumulation data set for each pixel of a frame. Preferably, each accumulation data set includes accumulated color data and a counter value. A Z buffer is included in the system, where the Z buffer stores Z data for each pixel of the frame. A drawing buffer stores a color data set for each pixel of the frame, where each color data set includes color data and a valid indication. A mask buffer includes a plurality of pixel block indicators, where each of the plurality of pixel block indicators corresponds to a plurality of pixels of the frame. When a pixel block indicator is set, pixels included in a corresponding plurality of pixels that have set valid indications in the drawing buffer are understood to have valid color data stored in the drawing buffer and valid Z data stored in the Z buffer.