Abstract: In accordance with an embodiment of the present invention a digital representation of a YCbCr video signal data stream is received that represents a video image or a series of video images. Received Y data values are linearly transformed and used to provide an RGB signal. The RGB signal is non-linearly adjusted to provide an adjusted RGB signal that enhances the viewed brightness of the data. In a specific embodiment, the non-linear adjusting adjusts the brightness of data near a mid-range of the video image more than other ranges of data.

Abstract: A lighting effect computation block and method therefore is presented. The lighting effect computation block separates lighting effect calculations for video graphics primitives into a number of simpler calculations that are performed in parallel but accumulated in an order-dependent manner. Each of the individual calculations is managed by a separate thread controller, where lighting effect calculations for a vertex of a primitive may be performed using a single parent light thread controller and a number of sub-light thread controllers. Each thread controller manages a thread of operation codes related to determination of the lighting parameters for the particular vertex. The thread controllers submit operation codes to an arbitration module based on the expected latency and interdependency between the various operation codes. The arbitration module determines which operation code is executed during a particular cycle, and provides that operation code to a computation engine.

Abstract: A method and apparatus for video compression that provides support for the inclusion of VBI data and copy protection data in an enhanced encoded video data stream is presented. A received video signal is separated such that a video data stream and a VBI data stream are produced. The video data stream is encoded to produce a compressed video data stream. The various types of VBI data that may be included in the VBI data stream are isolated, and one or more are selected for inclusion in the enhanced video data stream. The compressed video data stream is then combined with the one or more VBI data type streams to produce the enhanced video data stream. In other embodiments, copy protection information in the video signal is also detected and encoded such that it also can be included in the enhanced video data stream. The enhanced video data stream can be stored in memory or some other type of storage media for retrieval at a later time.

Abstract: A method and apparatus for allocation and control of memory bandwidth within a video graphics system is accomplished by first determining the memory bandwidth needs of each of the plurality of memory clients in the video graphics system. Based on this determination, a plurality of timers are configured, wherein each of the timers corresponds to one of the plurality of memory clients. The timers associated with the memory clients store two values. One value indicates the memory access interval for the corresponding client, which determines the spacing between memory access requests that can be issued by that particular client. The other value stored in the time is a memory access limit value, which determines the maximum length of a protected access to the memory by that particular client. A memory controller in the system receives requests from the plurality of clients and determines the priority of the different requests.

Abstract: A service chip for use with a computer. The chip includes a CPU interface, a transceiver interface, an adaptive echo cancellation filter, a monitor, and first and second data synthesizers. The CPU interface receives a transmit sample sequence from a modem sample generator executing on a central processor of the computer, and presents a receive sample sequence to a modem sample receiver executing on the central processor. The transceiver interface presents data to a line interface, which includes digital-to-analog and analog-to-digital converters for converting samples to/from analog signals for transmission on a telephone line. The filter adapts in response to an echo correlation between data transmitted over a transmit channel of the modem and data received on a receive channel of the transceiver interface. The monitor monitors the transmit sample sequence for a data starvation condition.

Abstract: A memory processing system and method for accessing memory in a graphics processing system are disclosed in which memory accesses are reordered. A memory controller arbitrates memory access requests from a plurality of memory requesters (referred to as “masters”). Reads are grouped together and writes are grouped together to avoid mode switching. Instructions are reordered to minimize page switches. In one embodiment, reads are given priority and writes are deferred. The memory accesses come from different masters. Each master provides memory access requests into its own associated request queue. The master provides page break decisions and other optimization information in its own queue. The masters also notify the memory controller of their latency requirements. The memory controller uses the queue and page break decisions to reorder the requests from all queues for efficient page and bank access while considering latency requirements. A sort queue may be used to reorder the requests.

Abstract: A method and apparatus for providing serial transmission of a parallel input is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from first and second current sources to a third current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.

Abstract: Multiple graphic images are generated simultaneously. An object or a polygon is received by a 3D graphics pipeline whereby a first stage of the pipeline performs a world transform on the modeling space of the object or polygon. An object culling is performed on the world space to eliminate objects not within view. Lighting is applied to the object as appropriate. Two view transforms are performed in parallel. Backface culling is applied to the resulting data. A single backface culling algorithm can be applied to both of the view transform scenes. A projection transformation is applied to those objects remaining following the backface culling. The first and second view transformed scenes are rendered in order to produce a first target image and a second target image respectively.

Abstract: A video graphics adapter is configured to provide both parallel and sequential color components to separate display monitors. When in a first state, the video graphics adapter provides individual color components to a video-output independent of each other color component, such that an entire frame of a red component will be provided to a video-out port for prior to, or subsequently after, an entire frame of the green component being provided to the video-out port. Each color component is provided to a common port. In response to a second configuration state, a traditional parallel red, green, blue (RGB) data port will be generated in order to provide data to a display device. In yet another configuration state, both the individual color components are provided at a common port, and the individual color components are provided in parallel to an RGB port.

Abstract: A method of graphics processing includes determining a non-depth conditional status and an occlusion status of a fragment. Such a method may be used in culling occluded fragments before expending resources such as processing cycles and memory bus usage. In one example, a scratchpad stores depth values of robust fragments and is used for occlusion testing. Graphics architectures, and methods that include use of representative Z values, are also disclosed.

Abstract: A duplex stainless steel including, in weight percent, up to 0.06 percent carbon, 15 up to less than 25 percent chromium, greater than 3 up to 6 percent nickel, up to 3.75 percent manganese, 0.14 up to 0.35 percent nitrogen, up to 2 percent silicon, greater than 1.4 up to less than 2.5 percent molybdenum, up to less than 0.5 percent copper, up to less than 0.2 percent cobalt, up to 0.05 percent phosphorous, up to 0.005 percent sulfur, and 0.001 up to 0.0035 percent boron, with the remainder being iron and incidental impurities is disclosed. The duplex stainless steel may be included in an article of manufacture, such as a strip, bar, plate, sheet, casting, tubing or piping. A method for making such a duplex stainless steel is also disclosed.

Abstract: A method and apparatus for simultaneously communicating data over a plurality of data links, such as a bus, determines initial logic levels of data to the output on each of the plurality of data links and changes the logic levels, such as inverting the data, of at least some of the data to produce logic level adjusted data in response to determining the initial logic level of the data to reduce switching transitions of simultaneously switched output data over the plurality of data links.

Abstract: A method and apparatus for displaying 3-D stereoscopic images is disclosed. A first stencil is used to filter a right eye image. A second stencil is used to filter a left eye image. Generally, the first and second stencil will have mutually exclusive active areas. The filtered left eye image and filtered right eye image are combined to form a single 3-D image having both images. The combined image is displayed on a conventional monitor, and viewed through the use of a pair or 3-D blue/red type lenses.

Abstract: A configurable vertex blending circuit that allows both morphing and skinning operations to be supported in dedicated hardware is presented. Such a configurable vertex blending circuit includes a matrix array that is used for storing the matrices associated with the various portions of the vertex blending operations. Vertex data that is received is stored in an input vertex buffer that includes multiple position buffers such that the multiple positions associated with morphing operations can be stored. Similarly, the single position typically associated with skinning operations can be stored in one of the position buffers. The input vertex buffer further stores blending weights associated with the various component operations that are included in the overall vertex blending operation. An arithmetic unit, which is configured and controlled by a transform controller, performs the calculations required for each of a plurality of component operations included in the overall vertex blending operation.

Abstract: A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory.

Abstract: The invention provides a method of generating cache indexes that reduces the likelihood that adjacent addresses will map to the same cache regions. The hashing process is optimized to be sensitive to small changes in the input data so that similar sets of input data will preferably not result in the same or even similar output data. Memory accesses of the sort performed when rendering graphical images may involve numerous accesses to relatively similar memory locations Therefore, hashing of the index values that determine where the information from the memory locations will be stored while that information is in cache decreases the likelihood of similar memory locations being stored at the same cache location. Consequently, cache efficiency and performance is improved.

Abstract: A device configuration method and apparatus initializes a device such as at least one graphics processor, by detecting whether the at least one graphics processor requires a dedicated address space. If the device requires a dedicated address space, boot up code, such as the system bios, maps the dedicated address space to another address space prior to running of an operating system. This is done based on, for example, using at least one subclass code bit in a class code register in configuration space memory as both a device function identifier and as control data to control mapping of the dedicated address space to another address space. The method and apparatus provides a type of universal method and apparatus for relocating or disabling, for example, VGA resources, through PCI registers or other suitable registers while maintaining legacy processing for graphics and video applications.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A method and apparatus for dynamic issuing of memory access instructions. In particular, a specific data access request that is about to be sent to a memory, such as a frame buffer, is dynamically chosen based upon pending requests within a pipeline. It is possible to optimize video data requests by dynamically selecting a memory access request at the time the request is made to the memory. In particular, if it is recognized that the memory about to be accessed will no longer be needed by subsequent memory requests, the request can be changed from a normal access request to an access request with an auto-close option. By using an auto close option, the memory bank being accessed is closed after the access, without issuing a separate memory close instruction.

Abstract: An impedance compensation circuit and method for an input/output buffer provides dynamic impedance compensation by using programmable impedance arrays and a dynamically adjustable on-chip load. Accordingly, among other advantages, only a single off-chip or external calibrated impedance resistor is used and only a single test pad is necessary.