Abstract: A pre-buffer voltage level shifting circuit includes a multi-supply voltage level shifting circuit having single gate oxide devices coupled to produce a pre-buffer output signal to an output buffer. The pre-buffer output signal has a level within normal gate voltage operating levels of the single gate oxide devices for each of the least a plurality of supply voltages. In one embodiment, the multi-supply voltage level shifting circuit includes a current mirror coupled to at least one of the first or second power supply voltage and also uses a non-linear device, such as a transistor configured as a diode, which is coupled to the output of current mirror. The non-linear device is coupled to receive a digital input signal from a signal source, such as from a section of core logic. A switching circuit coupled to the non-linear device selectively activates the non-linear device based on a level of the digital input signal.

Abstract: A method and apparatus for configuring multiple devices in a computer system is presented. Upon receipt of a device enumeration request corresponding to a first device, an indication that the first device is inoperable is returned. In response to a second device enumeration request corresponding to a second device, an indication of the capabilities of the second device is returned. When a configuration command corresponding to the second device is received, configuration information derived based on the configuration command is provided to both the first and second devices such that uniform parameter configuration is achieved with respect to the first and second devices. Because the operating system that issues the device enumeration request is informed that the first device is inoperable, the first device will be rendered unconfigurable and therefore configuration commands addressed to the first device will not be generated by the operating system.

Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter(DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state.

Abstract: A method for rendering polygons in a computer graphics system in which the computer display is divided into a plurality of subregions, and the rasterization process is performed in a micro framebuffer for each subregion, rather than sending raster data for each triangle into the frame buffer. Each polygon undergoes a first stage bounding box intersection test to identify the subregions which are likely to intersect with the polygon. If the number or configuration of intersected subregions exceeds a predetermined threshold requirement, then the polygon undergoes a more precise second stage intersection test to identify which subregions are actually intersected by the polygon. If the number or configuration of intersected subregions is below the threshold requirement, then the control data for the polygon is passed on to each of the identified subregions.

Abstract: A fluid separation assembly having a fluid permeable membrane and a wire mesh membrane adjacent the fluid permeable membrane, wherein the wire mesh membrane supports the fluid permeable membrane and is coated with an intermetallic diffusion barrier. The barrier may be a thin film containing at least one of a nitride, oxide, boride, silicide, carbide and aluminide. Several fluid separation assemblies can be used in a module to separate hydrogen from a gas mixture containing hydrogen.

Abstract: A method and apparatus for clearing memory, or portions thereof in a fast and efficient manner begins by representing a group of memory locations by a representative value. When a particular group of memory locations is accessed, a determination is made as to whether the corresponding representative value is in first state. If so, a clear value is stored in each corresponding memory location of a cache memory. Note that the corresponding memory locations of the cache memory correspond to the group of memory locations. The processing continues by setting a dirty bit for the corresponding memory locations of cache when the representative value is in the first state. If, however, the representative value is in a second state, data is read from the group of memory locations into the corresponding memory locations of the cache memory. When a cache write-back command is received, the data, or clear values, stored in memory are written from the cache memory into the main memory.

Abstract: A method of producing a nickel base alloy includes casting the alloy within a casting mold and subsequently annealing and overaging the ingot at at least 1200° F. (649° C.) for at least 10 hours. The ingot is electroslag remeelted at a melt rate of at least 8 lbs/min (3.63 kg/mm.), and the ESR ingot is then transferred to a heating furnace within 4 hours of complete solidification and is subjected to a novel post-ESR heat treatment. A suitable VAR electrode is provided form the ESR ingot, and the electrode is vacuum arc remelted at a melt rate of 8 to 11 lbs/minute (3.63 to 5.00 kg/minute) to provide a VAR ingot. The method allows premium quality VAR ingots having diameters greater than 30 inches (762 mm) to be prepared from Alloy 718 and other nickel base superalloys subject to significant segregation on casting.

Abstract: From a display memory, an image scaler retrieves display data representing an image, and produces a data stream representing a scaled version of the image. Based on the data stream, a digital-to-analog converter produces display signals suitable for displaying the scaled version on as a full-screen image on a display screen. Optionally, the scaled version is displayed in a window on the display screen. Characteristics of the scaled version are based on input signals intercepted from a keyboard and a pointing device by an input interception program. For a pointer displayed on the display screen for the pointing device, logical and visual pointer positions are determined based on the input signals and the characteristics of the scaled version.

Abstract: A 3-D graphics system combines a software programmed setup processor, a 3-D pipeline, and a software programmed back end processor. The setup processor performs “setup” on polygons for the 3-D pipeline. The 3-D pipeline rasterizes the polygons to create pixels. The back end processor performs back end processing, such as Z-buffering and alpha blending on the pixels. In one embodiment, the throughput of the 3-D graphics system is increased by clusterizing the pixels before back end processing. Specifically, a clusterizer combines pixels into clusters that can be processed by the back end processors without data coherency problems. Furthermore, the pixels are selected for a cluster to minimize memory latency and access times. In some embodiments, clusters are filled with fill addresses by a cluster filler. The filled addresses generated by the cluster filler, do not cause potential hazards in the back end processor.

Abstract: A method and apparatus for dependent segmentation and paging processing within a computer system include processing that begins by determining context of an operation supported by a native operating system. The context of an operation may correspond to performing an operation that is a native operating system operation or may be a legacy operating system operation. The processing then continues by setting within a corresponding segment descriptor a paging enable bit for a given segment that corresponds to the operation when the context of the operation corresponds to a legacy operating system. The setting of the paging enable bit is done in accordance with the processing of the native operating system. The processing then continues by processing the segment descriptor via segmentation processing in accordance with the legacy operating system to obtain a linear address. With the paging enable bitd, the linear address is processed to obtain a physical address.

Abstract: A bus interface control system and method includes an on-demand bus master interface for independently requesting multistream data from host memory without interrupting processing of the host processor between independent requests for data packets. A plurality of digital signal processors share the host bus and utilize flexible data speed transfer depending upon demand of real time data that must be transferred from host memory. The master interface control system includes an packet by packet arbitor to facilitate maximum throughput of data on-demand by the plurality of processing unit.

Abstract: An expansion card bracket and a method for manufacturing and utilizing the expansion card bracket. The bracket includes a primary surface that is adapted for mounting the bracket into a computer chassis. The primary surface is complemented with an appendage that extends rearward from the rear face of the primary surface. The appendage is formed such that it attaches to the expansion card at a recessed point and provides support to the primary surface of the bracket.

Abstract: A carry save multiplier receives two input values having respective bit lengths A and B and provides sum and carry values, each having bit lengths A+B+1. A carry prediction circuit receives the most significant bit of the sum and carry values and provides an extension bit to be merged with less significant bits of the sum and carry bits. A carry save adder receives the altered sum and carry values, as well as a third input value to provide second sum and carry values. The second sum and carry values are added in a carry propagate adder to form a resulting value. This allows for a faster multiplication to form a product, and the faster addition of this product to another value such as an accumulator value.

Abstract: A delay lock loop (DLL) circuit for generating a precisely delayed output signal relative to an input signal. The DLL circuit includes a phase detector for detecting a phase difference between the input signal and the DLL output signal, a lock circuit for detecting when the difference between the input signal and the output signal is zero, and a delay element control circuit for increasing and decreasing the phase of the output signal. This circuit design reduces processing delay, improves jitter performance, and extends the DLL operating frequency range.

Abstract: A method and apparatus for managing compressed Z information in a video graphics system that supports anti-aliasing is described. Each pixel in the display frame is represented with a primary Z value, a secondary Z value, a first and second color, and a pixel mask that indicates how the Z values and colors apply to the samples of the pixel. The primary Z values for the pixels in a pixel block are then compressed using a compression algorithm and stored in a Z buffer in a compressed format. A secondary mask that indicates which pixels in the pixel block have valid secondary Z values is also stored in the Z buffer, along with the secondary Z values and the pixel masks in an uncompressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates the level of compression of the Z information the corresponding pixel block.

Abstract: A method and apparatus is presented for combining multiple data elements to produce resultant data elements, where the data elements used for combination are reused after being loaded into memory on an integrated circuit. The apparatus includes a memory, where the memory stores a plurality of lines of data. The apparatus further includes a circular line buffer operably coupled to the memory, where the circular line buffer stores a plurality of line elements from a portion of the plurality of lines of data. A read addressing block operably coupled to the circular line buffer generates a number of read pointers corresponding to the circular line buffer. Each of the read pointers is used to address the circular line buffer to retrieve one of the data elements from a different line stored in the circular line buffer. A combination block combines the line elements selected by the read pointers to produce a result element.

Abstract: A video graphics system employs a method and apparatus for selectively providing drawing commands to a graphics processor to improve the processing efficiency of the system. The video graphics system includes a graphics driver, a graphics processor, and a memory. The graphics driver is operably coupled to an application that issues drawing commands to be processed by the video graphics system. Each drawing command includes an address of a location within the memory that includes vertex information for the vertices of one or more graphics primitives to be displayed on a display device operably coupled to the graphics processor. The vertex information is stored in the memory by the application prior to issuance of a drawing command referencing the location in memory of the stored vertex information.

Abstract: A method and apparatus for video decoding of compressed video data begins by generating a plurality of coefficients based on run level data of two-dimensional frequency components corresponding to the compressed video data. As the coefficients are generated, they are stored in a coefficient section of memory. Once the coefficients have been stored, they are utilized to generate intermediate results. As the intermediate results are being generated, they are stored in an intermediate section of the memory. Next, representations of the video data are generated based on the intermediate results and stored in an output section of the memory. The storing and retrieving of the coefficients, intermediate results, and representations of the video data are done in a time multiplexed manner.

Abstract: An I/O pad voltage protection circuit and method tracks a bias voltage of cascaded stages in order to avoid overvoltage stress in I/O transistors. An overshoot protection circuit controls overshoot current sinking to provide a clamp voltage equal to an I/O pad supply voltage, or other suitable reference voltage, during overshoot conditions, as a function of a reference voltage generated by a reference voltage generating circuit. An undershoot protection circuit includes a reference voltage generating circuit and controls undershoot current sinking to provide a clamp voltage approximately equal to an I/O pad ground voltage, or other suitable reference voltage, during undershoot conditions as a function of a reference voltage generated by the second reference voltage generating circuit.

Abstract: The present invention provides a method for improving playback consistency of an encoded video stream. The method of the present invention first determines whether a series of values of the progressive_frame flag of consecutive frames of the encoded video stream are arranged in a predetermined pattern. If the values are arranged in the predetermined pattern, an image of at least one of the frames is displayed progressively regardless of the value of the progressive_frame flag of that frame. As a result, the video stream is played back as if the movie had been consistently encoded in the first place.