Abstract: The present disclosure is directed a system and method for exploiting camera and depth information associated with rendered video frames, such as those rendered by a server operating as part of a cloud gaming service, to more efficiently encode the rendered video frames for transmission over a network. The method and system of the present disclosure can be used in a server operating in a cloud gaming service to improve, for example, the amount of latency, downstream bandwidth, and/or computational processing power associated with playing a video game over its service. The method and system of the present disclosure can be further used in other applications where camera and depth information of a rendered or captured video frame is available.

Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.

Abstract: A technique for efficient time-division of resources in a virtualized accelerated processing device (“APD”) is provided. In a virtualization scheme implemented on the APD, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD performs a virtualization context switch by stopping operations for a current virtual machine (“VM”) and starting operations for another VM. Typically, each VM is assigned a fixed length of time, after which a virtualization context switch is performed. This fixed length of time can lead to inefficiencies. Therefore, in some situations, in response to a VM having no more work to perform on the APD and the APD being idle, a virtualization context switch is performed “early.” This virtualization context switch is “early” in the sense that the virtualization context switch is performed before the fixed length of time for the time-slice expires.

Abstract: Embodiments of a peripheral component are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors in one peripheral component can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: The present disclosure is directed to techniques for determining a perceptual importance map. The perceptual importance map indicates the relative importance to the human visual system of different portions of an image. The techniques include obtaining cost values for the blocks of an image, where cost values are values used in determining motion vectors. For each block, a confidence value is derived from the cost values. The confidence value indicates the confidence with which the motion vector is believed to be correct. A perceptual importance value is determined based on the confidence value via one or more modifications to the confidence value to better reflect importance to the human visual system. The generated perceptual importance values can be used for various purposes such as allocating bits for encoding, identifying regions of interest, or selectively rendering portions of an image with greater or lesser detail based on relative perceptual importance.

Abstract: A technique for varying firmware for different virtual functions in a virtualized device is provided. The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function. To vary the firmware, each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function. The addresses for the firmware are provided by a corresponding virtual machine at configuration time.

Abstract: A method and apparatus for rate control for a constant-bit-rate finite-buffer-size video encoder is described. Rate control is provided by adjusting the size of non-intra frames based on the size of intra frames. A sliding window approach is implemented to avoid excessive adjustment of non-intra frames located near the end of a group of pictures. A measurement of “power” based on a sum of absolute values of pixel values is used. The “power” measurement is used to adjust a global complexity value, which is used to adjust the sizes of frames. The global complexity value responds to scene changes. An embodiment of the invention calculates and uses L1 distances and pixel block complexities to provide rate control. An embodiment of the invention implements a number of bit predictor block. Predictions may be performed at a group-of-pictures level, at a picture level, and at a pixel block level. An embodiment of the invention resets a global complexity parameter when a scene change occurs.

Abstract: A processor is configured to store color component values associated with a first subset of vertices of a three-dimensional (3-D) look up table (LUT) in a first subset of memory elements. The color component values are defined according to a destination gamut. A data select module is configured to access the color component values from the first subset of the memory elements concurrently with the processor storing color component values associated with a second subset of the vertices of the 3-D LUT in a second subset of the memory elements. The data select module is configured to access the color component values from the first and second subsets of the memory elements in response to the processor storing the color component values associated with the second subset of the vertices of the 3-D LUT in the second subset of the memory elements. This process can be extended to additional subsets.

Abstract: Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.

Abstract: Methods of refining the grain size of titanium and titanium alloys include multiple upset and draw forging. Titanium and titanium alloy workpieces are heated to a workpiece forging temperature within a workpiece forging temperature range in the alpha+beta phase field. The workpiece may comprise a starting cross-sectional dimension. The workpiece is upset forged in the workpiece forging temperature range. After upsetting, the workpiece is multiple pass draw forged in the workpiece forging temperature range. Multiple pass draw forging may comprise incrementally rotating the workpiece in a rotational direction followed by draw forging the workpiece after each incremental rotation. Incrementally rotating and draw forging the workpiece is repeated until the workpiece comprises substantially the same starting cross-sectional dimension.

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that receives a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one of a plurality of virtual memory pools to produce a mapping result, and providing the mapping result to the processor.

Abstract: Virtual Reality (VR) systems, apparatuses and methods of processing data are provided which include predicting, at a server, a user viewpoint of a next frame of video data based on received user feedback information sensed at a client, rendering a portion of the next frame using the prediction, encoding the portion, formatting the encoded portion into packets and transmitting the video data. At a client, the encoded and packetized A/V data is received and depacketized. The portion of video data and corresponding audio data is decoded and controlled to be displayed and aurally provided in synchronization. Latency may be minimized by utilizing handshaking between hardware components and/or software components such as a 3D server engine, one or more client processors, one or more client processors, a video encoder, a server NIC, a video decoder, a client NIC; and a 3D client engine.

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad.

Abstract: Metastable beta titanium alloys and methods of processing metastable ?-titanium alloys are disclosed. For example, certain non-limiting embodiments relate to metastable ?-titanium alloys, such as binary ?-titanium alloys comprising greater than 10 weight percent molybdenum, having tensile strengths of at least 150 ksi and elongations of at least 12 percent. Other non-limiting embodiments relate to methods of processing metastable ?-titanium alloys, and more specifically, methods of processing binary ?-titanium alloys comprising greater than 10 weight percent molybdenum, wherein the method comprises hot working and aging the metastable ?-titanium alloy at a temperature below the ?-transus temperature of the metastable ?-titanium alloy for a time sufficient to form ?-phase precipitates in the metastable ?-titanium alloy. The metastable ?-titanium alloys are not solution heat treated after hot working and prior to aging.

Abstract: A force/torque sensor comprising a Tool Adapter Plate (TAP) connected to a Mounting Adapter Plate (TAP) by one or more radially-spaced, deformable beams features a pair of strain gages affixed to only one surface of each beam. The two strain gages are affixed to, e.g., the top surface on either side of, and spaced away from, a neutral axis of the beam. This enables a very compact sensor design, in one embodiment, machined from a single piece of metal stock. The two sensors may be connected in a quarter bridge topology. In one embodiment, another pair of strain gages is affixed to the same side of the beam, and the four gages are wired in a half-bridge topology.

Abstract: A three-dimensional (3-D) look up table (LUT) can be accessed using an address decoder to identify a plurality of vertices in the 3-D LUT based on a number (m) of most significant bits (MSBs) of three coordinate values representative of a first color and a non-zero integer (p). The three coordinate values are determined by a source gamut. One or more memories store component values representative of a plurality of second colors determined by a destination gamut. The component values are stored at memory locations associated with the plurality of vertices. An interpolator maps the input color to an output color in the destination gamut based on the component values.

Abstract: A method for reducing impurities in magnesium comprises: combining a zirconium-containing material with a molten low-impurity magnesium including no more than 1.0 weight percent of total impurities in a vessel to provide a mixture; holding the mixture in a molten state for a period of time sufficient to allow at least a portion of the zirconium-containing material to react with at least a portion of the impurities and form intermetallic compounds; and separating at least a portion of the molten magnesium in the mixture from at least a portion of the intermetallic compounds to provide a purified magnesium, wherein the purified magnesium includes an increased level of zirconium compared to the low-impurity magnesium, wherein the purified magnesium includes greater than 1000 ppm zirconium, and wherein the purified magnesium includes a reduced level of impurities other than zirconium compared to the low-impurity magnesium.

Abstract: An apparatus and method provides temporal image processing by producing, for output on a single link such as a single cable or wireless interface, packet based multi-steam information wherein one stream provides at least frame N information for temporal imaging processing and a second stream that provides frame N?1 information for the same display, such as a current frame and a previous frame or a current frame and next frame. The method and apparatus also outputs the packet based multi-stream information and sends it for the same display for use by the same display so that the receiving display may perform temporal image processing using the multi-stream multi-frame information sent with a single link.

Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.