Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.

Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.

Abstract: A method of producing an article selected from a titanium article and a titanium alloy article comprises melting feed materials with a source of hydrogen to form a molten heat of titanium or a titanium alloy, and casting at least a portion of the molten heat to form a hydrogenated titanium or titanium alloy ingot. The hydrogenated ingot is deformed at an elevated temperature to form a worked article comprising a cross-sectional area smaller than a cross-sectional area of the hydrogenated ingot. The worked article is dehydrogenated to reduce a hydrogen content of the worked article. In certain non-limiting embodiments of the method, the dehydrogenated article comprises an average ?-phase particle size of less than 10 microns in the longest dimension.

Abstract: A video server generates metadata representative of interpolation parameters for portions of a first frame representative of a scene in a stream of frames including the first frame. The interpolation parameters are used to generate at least one interpolated frame representative of the scene subsequent to the first frame and prior to a second frame in the stream of frames. The video server incorporates the metadata into the stream and transmits the stream including the multiplexed metadata. A video client receives the first frame representative the stream of frames including the metadata. The video client generates one or more interpolated frames representative of the scene subsequent to the first frame and prior to a second frame in the stream of frames based on the first frame and the metadata. The video client displays the first frame, the one or more interpolated frames, and the second frame.

Abstract: Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymer layer to a passivation structure of a semiconductor workpiece where the semiconductor workpiece has first and second semiconductor chips separated by a dicing street. A first opening is patterned in the polymer layer with opposing edges pulled back from the dicing street. A mask is applied over the first opening. A first portion of the passivation structure is etched while using the polymer layer as an etch mask.

Abstract: A modular approach to an electrical power and/or signal passing utility module is presented. A universal receptacle is fixedly disposed in bores in both of first and second signal connector blocks. A threaded socket member and a nonconductive guide bushing are installed, as needed, in receptacles in the first block, and a threaded pin member is installed in corresponding receptacles in the second block. The nonconductive guide bushing insulates the sockets, and guides pin posts into the socket as the two blocks abut. A compliant member such as an o-ring provides compliance of the socket and pin assemblies in the signal connector blocks, making the assemblies self-aligning. The socket and pin assemblies are field-replaceable by use of a simple tool.

Abstract: An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Abstract: Described herein are a method and device for transferring data in a computer system. The device includes a host processor, a plurality of first memory architectures, a switch, a redundant array of independent drives (RAID) assist unit; and a second memory architecture. The host processor is configured to send a data transfer command to the RAID assist unit via the switch. The RAID assist unit is configured to create a set of parallel memory transactions between the plurality of first memory architectures and the second memory architecture, execute the set of parallel memory transactions via the local switch and absent interaction with the host processor; and notify the host processor upon completion of data transfer. In an implementation, the plurality of first memory architectures is non-volatile memories (NVMs) and the second memory architecture is local memory.

Abstract: An austenitic stainless steel having low nickel and molybdenum and exhibiting comparable corrosion resistance and formability properties to higher nickel and molybdenum alloys comprises, in weight %, up to 0.20 C, 2.0-9.0 Mn, up to 2.0 Si, 16.0-23.0 Cr, 1.0-5.0 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.1-0.35 N, up to 4.0 W, up to 0.01 B, up to 1.0 Co, iron and impurities, the steel having a ferrite number of less than 10 and a MD30 value of less than 20° C.

Abstract: One embodiment of a method of refining alpha-phase grain size in an alpha-beta titanium alloy comprises working an alpha-beta titanium alloy at a first working temperature within a first temperature range in the alpha-beta phase field of the alpha-beta titanium alloy. The alloy is slow cooled from the first working temperature. On completion of working at and slow cooling from the first working temperature, the alloy comprises a primary globularized alpha-phase particle microstructure. The alloy is worked at a second working temperature within a second temperature range in the alpha-beta phase field. The second working temperature is lower than the first working temperature. The is worked at a third working temperature in a third temperature range in the alpha-beta phase field. The third working temperature is lower than the second working temperature. After working at the third working temperature, the titanium alloy comprises a desired refined alpha-phase grain size.

Abstract: An alloy is disclosed comprising up to 0.05 weight percent carbon, 27.0 to 31.0 weight percent chromium, up to 0.5 weight percent copper, 7.0 to 11.0 weight percent iron, up to 0.5 weight percent manganese, up to 0.015 weight percent sulfur, up to 0.5 weight percent silicon, at least 58 weight percent nickel, and incidental impurities, wherein the alloy exhibits an ASTM grain size of 3.0 to 9.0, exhibits a uniform grain size distribution, includes intergranular M23C6 carbide precipitates uniformly distributed on grain boundaries, and includes minimal or no intragranular M23C6 carbide precipitates. Articles of manufacture including the alloy also are described.

Abstract: The present disclosure is directed to techniques for determining variance of a pixel block in a frame of video based on variance of pixel blocks in a reference frame of the video, instead of directly, for example, by calculating variance based on pixel values of the pixel block. The techniques include identifying a motion vector for a pixel block in a current frame, the motion vector pointing to a pixel block in a reference frame. The techniques also include determining the cost associated with the motion vector and comparing the cost to first and second thresholds. The techniques include determining the variance for the pixel block of the current frame based on the comparison of the cost to the first and second threshold and based on the variance of the pixel block of the reference frame.

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

Abstract: Systems, apparatuses, and methods for migrating memory pages are disclosed herein. In response to detecting that a migration of a first page between memory locations is being initiated, a first page table entry (PTE) corresponding to the first page is located and a migration pending indication is stored in the first PTE. In one embodiment, the migration pending indication is encoded in the first PTE by disabling read and write permissions. If a translation request targeting the first PTE is received by the MMU and the translation request corresponds to a read request, a read operation is allowed to the first page. Otherwise, if the translation request corresponds to a write request, a write operation to the first page is blocked and a silent retry request is generated and conveyed to the requesting client.

Abstract: A processing apparatus is provided that includes an encoder configured to encode current frames of video data using previously encoded reference frames and perform motion searches within a search window about each of a plurality of co-located portions of a reference frame. The processing apparatus also includes a processor configured to determine, prior to performing the motion searches, which locations of the reference frame to reload the search window according to a threshold number of search window reloads using predicted motions of portions of the reference frame corresponding to each of the locations. The processor is also configured to cause the encoder to reload the search window at the determined locations of the reference frame and, for each of the remaining locations of the reference frame, slide the search window in a first direction indicated by the location of the next co-located portion of the reference frame.

Abstract: A video source, a display and a method of processing multilayered video are disclosed. The video source decodes a multilayered video bit stream to transmit synchronized streams of decompressed video images and corresponding overlay images to an interconnected display. The display receives separate streams of video and overlay images. Transmission and reception of corresponding video and overlay images is synchronized in time. A video image received in the display can be selectively processed separately from its corresponding overlay image. The video image as processed at the display is later composited with its corresponding overlay image to form an output image for display.

Abstract: A single source image encoder encodes more than one display stream, such as multiple display streams each for a different display or multiple display streams for the same display, using multiple index color history (ICH) buffers. As applied to a DSC encoder, the same DSC encoder is used to encode more than one DSC compliant display stream. Multiple encoded display bitstreams are output as multiple display data streams to a plurality of displays. Such a configuration can significantly reduce the area cost of an integrated circuit that employs an image encoder since additional encoders are eliminated.

Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.

Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.

Abstract: A method for allocating registers in a compute unit of a vector processor includes determining a maximum number of registers that are to be used concurrently by a plurality of threads of a kernel at the compute unit. The method further includes setting a mode of register allocation at the compute unit based on a comparison of the determined maximum number of registers and a total number of physical registers implemented at the compute unit.