Abstract: A method and apparatus are described for controlling depth and power consumption of a first-in first-out (FIFO) memory including a data storage, a FIFO top register, a FIFO bottom register and control logic. The data storage may be segmented into a plurality of data storage segments. The FIFO top register may be configured to generate a first value indicating where a first entry in the data storage is stored. The FIFO bottom register may be configured to generate a second value indicating where a last entry in the data storage is stored. The control logic may be configured to determine which of the data storage segments to activate or deactivate based at least in part on the first and second values, and to monitor an available capacity and a write/read rate of the FIFO memory as data is read from and written to the activated data storage segments.

Abstract: Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.

Abstract: The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: An apparatus includes a first sensing circuit operative to drive a node with a first sample of an input signal during a first phase of a clock signal. The apparatus includes a second sensing circuit operative to drive the node with a second sample of the input signal during a second phase of the clock signal. An output signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal. N is an integer greater than one. In at least one embodiment of the apparatus, during the second phase of the clock signal, the first sensing circuit provides a high impedance to the node, and during the first phase of the clock signal, the second sensing circuit provides a high impedance to the node.

Abstract: An austenitic stainless steel composition including relatively low nickel and molybdenum levels, and exhibiting corrosion resistance, resistance to elevated temperature deformation, and formability properties comparable to certain alloys including higher nickel and molybdenum levels. Embodiments of the austenitic stainless steel include, in weight %, up to 0.20 C: 2.0 to 9.0 Mn, up to 2.0 Si, 16.0 to 23.0 Cr, 1.0 to 7.0 Ni. up to 3.0 Mo, up to 3.0 Cu, 0.05 to 0.35 N, up to 4.0 W, (7.5(C))?(Nb+Ti+V+Ta+Zr)?1.5, up to 0.01 B, up to 1.0 Co, iron and impurities. Additionally, embodiments of the steel may include 0.5?(Mo+W/2)?5.0 and/or 1.0?(Ni+Co)?8.0.

Abstract: A forging die heating or preheating apparatus comprises a burner head comprising a plurality of flame ports. The burner head is oriented to compliment an orientation of at least a region of a forging surface of a forging die and is configured to receive and combust a supply of an oxidizing gas and a supply of a fuel and produce flames at the flame ports. The plurality of flame ports are configured to impinge the flames onto the forging surface of the forging die to substantially uniformly heat at least the region of the forging surface of the forging die.

Abstract: An aspect of the present disclosure is directed to low-alloy steels exhibiting high hardness and an advantageous level of multi-hit ballistic resistance with low or no crack propagation imparting a level of ballistic performance suitable for military armor applications. Various embodiments of the steels according to the present disclosure have hardness in excess of 550 BHN and demonstrate a high level of ballistic penetration resistance relative to conventional military specifications.

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes a first conductor structure. A first via is formed in the first interconnect layer and in electrical contact with the first conductor structure. The first via has a first oval footprint.

Abstract: Methods of refining the grain size of a titanium alloy workpiece include beta annealing the workpiece, cooling the beta annealed workpiece to a temperature below the beta transus temperature of the titanium alloy, and high strain rate multi-axis forging the workpiece. High strain rate multi-axis forging is employed until a total strain of at least 1 is achieved in the titanium alloy workpiece, or until a total strain of at least 1 and up to 3.5 is achieved in the titanium alloy workpiece. The titanium alloy of the workpiece may comprise at least one of grain pinning alloying additions and beta stabilizing content effective to decrease alpha phase precipitation and growth kinetics.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: Circuitry, apparatus and methods provide flicker detection and improved image generation for digital cameras that employ image sensors. In one example, circuitry and methods are operative to compare a first captured frame with a second captured frame that may be, for example, sequential and consecutive or non-consecutive if desired, to determine misalignment of scene content between the frames. A realigned second frame is produced by realigning the second frame with the first frame if the frames are determined to be misaligned. Luminance data from the realigned second frame and luminance data from the pixels of the first frame are used to determine if an undesired flicker condition exists. If an undesired flicker condition is detected, exposure time control information is generated for output to the imaging sensor that captured the frame, to reduce flicker. This operation may be done, for example, during a preview mode for a digital camera, or may be performed at any other suitable time.

Abstract: A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed.

Abstract: One of a video source device and a video sink device may: (a) deactivate a video processing function at the one device and send a command for causing the other of the video source device and the video sink device to activate the video processing function; (b) activate the video processing function at the one device and send a command for causing the other device to deactivate the video processing function; and (c) based on user input indicating whether (a) or (b) resulted in a preferred video image, effect (a) or (b). The one device may receive an indication of video processing functions of which the other device is capable, such that (a), (b) and (c) may be performed for each indicated video processing function of which the one device is also capable. A user interface including at least one selectable control for indicating whether a video image resulting from (a) or (b) is preferred may be displayed.

Abstract: A multiprocessor system includes a plurality of special purpose processors that perform different portions of a related processing task. A set of commands that cause each of the processors to perform the portions of the related task are distributed, and the set of commands includes a predicated execution command that precedes other commands within the set of commands. It is determined whether commands subsequent to the predicated execution command are intended to be executed by a first processor or a second processor based on information in the predicated execution command and the set of commands includes all commands to be executed by each processor.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.

Abstract: An austenitic stainless steel having low nickel and molybdenum and exhibiting comparable corrosion resistance and formability properties to higher nickel and molybdenum alloys comprises, in weight %, up to 0.20 C, 2.0-9.0 Mn, up to 2.0 Si, 16.0-23.0 Cr, 1.0-5.0 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.1-0.35 N, up to 4.0 W, up to 0.01 B, up to 1.0 Co, iron and impurities, the steel having a ferrite number of less than 10 and a MD30 value of less than 20° C.

Abstract: A method and system are described for low-latency video. In the method a frame, selected from a group of frames, is divided into P-regions and an I-region based on an assigned refresh pattern in a refresh loop. An I-region bit budget and a P-region bit budget are determined. Quantization parameters are determined using the I-region bit budget and the P-region bit budget. Macroblocks of the selected frame are encoded based on the quantization parameters. The I-complexity and P-complexity are updated and a new frame bit budget is determined. The dividing, determining of the I-region bit budget, determining of the P-region bit budget, determining of quantization parameters and encoding are repeated for each remaining frame in the group of frames.

Abstract: Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

Abstract: A method and apparatus for protecting access to audio and/or video data is accomplished when data is received, where the data may be audio data and/or video data. Having received the data, it is interpreted to determine whether an embedded data access parameter is active. If so, an indication of the particular type of data access is generated. The data access parameter may control access to the data as at least one of: copy restrictions, viewing restrictions, and/or use restrictions. The indication is subsequently provided to a computer system such that unauthorized accessing, including unauthorized copying, of the video and/or audio data is prohibited.