Patents Assigned to ATI
  • Patent number: 8387228
    Abstract: A method for producing a single-clad or multiple-clad product includes providing a welded assembly comprising a cladding material disposed on a substrate material. Both the substrate material and the cladding material are individually selected alloys. At least a first edge of the cladding material of the welded assembly does not extend to a first edge of the substrate material and thereby provides a margin between the first edges. A material that is an alloy having hot strength greater than the cladding material is within the margin and adjacent the first edge of the cladding material. The welded assembly is hot rolled to provide a hot rolled band, and the material within the margin inhibits the cladding material from spreading beyond the edge of the substrate material during the hot rolling. In certain embodiments of the methods, the substrate material is stainless steel and the cladding material is nickel or a nickel alloy.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: March 5, 2013
    Assignee: ATI Properties, Inc.
    Inventors: David S. Bergstrom, Kris J. Schott, Mark A. Tarhay
  • Patent number: 8389340
    Abstract: Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: March 5, 2013
    Assignee: ATI Technologies ULC
    Inventors: Roden R. Topacio, Neil McLellan
  • Publication number: 20130050572
    Abstract: A method and apparatus adaptively creates a dropped frame rate converted frame from a plurality of source frames using at least one alternate support frame in lieu of neighboring source frame, in response to corrupted picture identification information. Stated another way, a frame rate converter, in response to corrupted picture indication information, replaces at least one corrupted source frame with a temporally modified frame created from at least one alternate source frame. The corrupted picture identification information indicates that a source frame, or segment thereof, includes at least one corrupted or dropped source frame (or segment thereof). Accordingly, although a source frame has been dropped or is corrupted, the frame rate converter does not base its output on a repeated frame or a corrupted frame output by a decoder and instead utilizes other non-neighboring source images as though they were neighboring frames, instead of using a repeated frame or corrupted frame.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Philip L. Swan, Stephen J. Orr
  • Publication number: 20130050448
    Abstract: Circuitry for better integrating multiview-based 3D display technology with the human visual system includes logic that identifies an object of interest from a plurality of objects in a multiview-based 3D scene displayed on one or more displays and provides focus adjustment control data for eyewear to view the 3D scene based on perceived distance data corresponding to the identified at least one object of interest and the identified at least one object of interest. In one example, the circuitry includes logic that determines the perceived distance data corresponding to the at least one object of interest based on inter-object distance data indicating a horizontal offset between the at least one object of interest in a first scene view and the same at least one object of interest in a second scene view and display distance data indicating the distance between one or more display screens and a viewing position. Related methods are also set forth.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: ATI Technologies ULC
    Inventor: Philip L. Swan
  • Publication number: 20130054851
    Abstract: A method and a device for disabling a lower version of a computer bus and interconnection protocol (e.g., Peripheral Component Interconnect Express (PCIe) 2.0 or higher) for interoperability with a receiver compliant to a lower version of the protocol are disclosed. The device detects a presence of a receiver, and starts link training. During the link training, the number of link training failures or the elapsed time is counted. The device transmits a training sequence including symbols set in accordance with a higher version of the protocol that the device supports on each lane that the receiver is detected as long as the number of link training failures or the elapsed time is below a predetermined threshold. If the number of link training failures or the elapsed time reaches a predetermined threshold, the device transmits a training sequence including symbols set in accordance with a lower version of the protocol.
    Type: Application
    Filed: October 29, 2012
    Publication date: February 28, 2013
    Applicant: ATI TECHNOLOGIES, ULC
    Inventor: ATI TECHNOLOGIES, ULC
  • Publication number: 20130050414
    Abstract: A method and system are provided for navigating and selecting objects within a 3D video image by computing a depth coordinate based upon two-dimensional (2D) image information from left and right views of such objects. In accordance with preferred embodiments, commonly available computer navigation devices and input devices can be used to achieve such navigation and object selection.
    Type: Application
    Filed: August 24, 2011
    Publication date: February 28, 2013
    Applicant: ATI Technologies ULC
    Inventors: Pavel Siniavine, Jitesh Arora, Alexander Zorin, Gabor Sines, Xingping Cao, Philip L. Swan, Mohamed K. Cherif, Edward Callway
  • Patent number: 8381563
    Abstract: A forging die heating or preheating apparatus comprises a burner head comprising a plurality of flame ports. The burner head is oriented to compliment an orientation of at least a region of a forging surface of a forging die and is configured to receive and combust a supply of an oxidizing gas and a supply of a fuel and produce flames at the flame ports. The plurality of flame ports are configured to impinge the flames onto the forging surface of the forging die to substantially uniformly heat at least the region of the forging surface of the forging die.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: February 26, 2013
    Assignee: ATI Properties, Inc.
    Inventors: Urban J. De Souza, Robin M. Forbes-Jones, Billy B. Hendrick, Alonzo L. Liles, Ramesh S. Minisandram, Sterry A. Shaffer
  • Patent number: 8384424
    Abstract: An averaged impedance calibration is obtained by utilizing two separately controlled resistive loads arranged in parallel and choosing two adjacent control codes to configure switch arrays to set the resistance of each of the separate resistive loads. The resistance of the resistive loads is averaged to provide greater accuracy. The two adjacent control codes are close to the target impedance value and typically one is slightly higher and one is slightly lower than the target impedance value.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: February 26, 2013
    Assignee: ATI Technologies ULC
    Inventor: Junho J. H. Cho
  • Patent number: 8384479
    Abstract: An amplifier circuit includes a first stage and a second stage. The first stage includes a differential input circuit coupled to a differential input node. The first stage includes a first partial cascode circuit including devices of a first type, the first partial cascode circuit being coupled to a first power supply node, a first bias node, and the differential input stage. The first stage includes a second partial cascode circuit including devices of a second type, the second partial cascode circuit being coupled to a second power supply node and the differential input circuit. The second stage is coupled to the first stage. The second stage includes a first full cascode circuit coupled to an output node.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: February 26, 2013
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Saeed Abbasi, Nima Gilanpour, Vincent Law
  • Patent number: 8386687
    Abstract: A method and apparatus for data transfer includes receiving a first data packet across a first bi-directional bus and receiving a second data packet across a second bi-directional bus. Next, the first data packet is written to a first register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is written to a second register operably coupled to the first bi-directional bus and the second bi-directional bus. The second data packet is then transferred across the first bi-directional bus and the first data packet is transferred across the second bi-directional bus, thereby providing data transfer across a plurality of bi-directional buses and providing for data to be transferred across those buses to be stored at an intermediate register so that the data may be transferred in the next clock cycle, overcoming any latency requirements.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 26, 2013
    Assignee: ATI Technologies ULC
    Inventors: Stephen L. Morein, Robert W. Bloemer
  • Patent number: 8378471
    Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: February 19, 2013
    Assignee: ATI Technologies ULC
    Inventors: Roden R. Topacio, Vincent Chan, Fan Yeung
  • Patent number: 8377409
    Abstract: Methods for making brines may generally comprise forming a mixture comprising: (i) a solid material produced as a by-product of the Kroll process including solid anhydrous magnesium chloride and solid elemental magnesium; (ii) an amount of a previously-produced brine; and (iii) an amount of water sufficient to provide a predetermined brine concentration. At least a portion of the solid material in the mixture is dissolved while simultaneously controlling the temperature of the mixture. At least a portion of insoluble matter is separated from the mixture.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: February 19, 2013
    Assignee: ATI Properties, Inc.
    Inventor: James A. Sommers
  • Publication number: 20130040067
    Abstract: Processes, systems, and apparatuses are disclosed for forming products from atomized metals and alloys. A stream of molten alloy and/or a series of droplets of molten alloy are produced. The molten alloy is atomized to produce electrically-charged particles of the molten alloy by impinging electrons on the stream of molten alloy and/or the series of droplets of molten alloy. The electrically-charged molten alloy particles are accelerated with at least one of an electrostatic field and an electromagnetic field. The accelerating molten alloy particles are cooled to a temperature that is less than a solidus temperature of the molten alloy particles so that the molten alloy particles solidify while accelerating. The solid alloy particles are impacted onto a substrate and the impacting particles deform and metallurgically bond to the substrate to produce a solid alloy preform.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: ATI Properties, Inc.
    Inventors: Richard L. Kennedy, Robin M. Forbes Jones
  • Patent number: 8373709
    Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 12, 2013
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Shahin Solki, Stephen Morein, Mark S. Grossman
  • Publication number: 20130032941
    Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
    Type: Application
    Filed: October 8, 2012
    Publication date: February 7, 2013
    Applicant: ATI TECHNOLOGIES ULC
    Inventor: ATI Technologies ULC
  • Publication number: 20130026819
    Abstract: A vehicle track-module including an upper drive wheel, a plurality of idler and bogey wheels, and an endless rubber track with spaced lugs which extends around the wheels and is driven by the drive wheel, which has: a middle main plate with a outer edge of first diameter and inward and outward sides forming the exposed inward and outward surfaces of the drive wheel; drive members axially across and projecting radially beyond the main-plate edge to a second diameter, each drive member having axially inward and outward end portions, a middle portion affixed at its middle position to the main-plate edge, and an outer track-engaging surface; and a rigidity ring affixed to the inward end portions of the drive members and having an inner diameter no less than half the first diameter and an outer diameter no greater than the second diameter. In some embodiments, the axial dimension of the track-engaging surfaces of the drive members is at least 50% greater than the axial dimension of the track lugs.
    Type: Application
    Filed: July 28, 2011
    Publication date: January 31, 2013
    Applicant: ATI, Inc.
    Inventors: Jamsheed Reshad, Duane Tiede
  • Patent number: 8361254
    Abstract: Maraging steel compositions, methods of forming the same, and articles formed therefrom comprising, by weight, 15.0 to 20.0% Ni, 2.0 to 6.0% Mo, 3.0 to 8.0% Ti, up to 0.5% Al, the balance Fe and residual impurities. The composition may be a first layer of a composite plate, and may have a second layer deposited on the first layer, the second layer having a composition comprising, by weight, 15.0 to 20.0% Ni, 2.0 to 6.0% Mo, 1.0 to 3.0 Ti, up to 0.5% Al, the balance Fe and residual impurities. The first layer may have a hardness value ranging from 58 to 64 RC, and the second layer may have a hardness value ranging from 48 to 54 RC. The first layer may be formed employing powdered metallurgical techniques. Articles formed from the compositions include armored plate.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: January 29, 2013
    Assignee: ATI Properties, Inc.
    Inventors: Ronald E. Bailey, Thomas R. Parayil, Timothy M. Hackett, Tong C. Lee
  • Publication number: 20130009980
    Abstract: A method and a processor for implementing the method are disclosed for processing of an image. A first algorithm is selected to be used for processing information representing an area of interest in the image. A second algorithm is selected to be used for processing information representing an area of the image that is not in the area of interest. The first and second algorithms are applied to their respective portions of the information representing the image.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Applicant: ATI TECHNOLOGIES ULC
    Inventor: Hao Ran Gu
  • Publication number: 20130010168
    Abstract: A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a display serial interface protocol, and a uni-directional serial link which accords to a camera serial interface protocol. The GMIC receives packets from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a host memory operation and may be connected to a display over a bi-directional serial link and to a camera over a uni-directional serial link and a bi-directional control link allowing the host to control the display and camera.
    Type: Application
    Filed: June 13, 2012
    Publication date: January 10, 2013
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Fariborz Pourbigharaz, Sergiu Goma, Milivoje Aleksic, Andrzej Mamona
  • Publication number: 20130009970
    Abstract: Apparatus and methods for reducing power consumption of a data transfer interface in a computer system are disclosed. In one embodiment, a method for reducing power consumption of a data transfer interface between a first device and a second device, includes, identifying a free interval between a first data and a second data, disabling the data transfer interface during the free interval, enabling the data transfer interface at the end of the free interval, and transmitting the second data. The method may also include a step of notifying the second device that the data transfer interface is being temporarily disabled. Another embodiment, for example, includes the transfer of display data (or video frames) over an interface, such as, a DisplayPort interface, between a graphics controller device and a timing controller device in a computer system.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: ATI Technologies ULC
    Inventor: Collis Quinn Troy Carter