Abstract: A method includes detecting one of an application access or a file type access, and configuring, in response to detecting the application or file type access, automatically without user interaction, a display system in an image quality configuration for the application or the file type where the image quality configuration is based on providing best image quality with respect to the application or the file type. Configuring the display system in an image quality configuration, may involve determining that a profile associated with the application or associated with the file type is stored in memory, and configuring the display system according to the profile. The method may adjust at least one anti-aliasing parameter or at least one anisotropic filter parameter. The method may monitor an operating system to obtain an indication that an application has been accessed or that a file type has been accessed.

Abstract: Methods and apparatus for accelerating the processing of image data are disclosed that are particularly useful in conducting graphical pattern searches. Embodiments of the invention conduct and implement comparative calculations of reference and search image pel data on a multi-pel comparative basis, particularly, sum of the absolute differences (SAD) based calculation comparisons.

Abstract: A method of manufacturing semiconductor packages at the wafer level is disclosed. A wafer has multiple integrated circuits (ICs) formed on its active surface, with each IC in communication with a plurality under-bump metallization (UBM) pads formed on one surface the package. The UBM pads include a larger pads near the center of package and smaller UBM pads near the periphery. The method includes attaching a stiffener to an inactive surface of the wafer; forming under bump metallization pads; and forming solder bumps extending from the UBM pads.

Abstract: Embodiments of a method and system for intra-prediction in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which units of video data in a frame are to be processed using an intra-prediction operation. In an embodiment, intra-prediction is performed on a frame basis such that intra-prediction is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the intra-prediction such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Abstract: A method includes generating, from a representation of a first integrated circuit, a representation of a second integrated circuit. The representation of the first integrated circuit includes a plurality of representations of operative memory channel interfaces including a representation of a first operative memory channel physical interface. The representation of the second integrated circuit includes a representation of a pseudo-memory channel physical interface and at least a representation of a second operative memory channel physical interface. The generating includes replacing an instantiation of a first circuit of the representation of the first operative memory channel physical interface with an instantiation of a second circuit. The instantiation of the second circuit is a representation of a circuit that is logically equivalent to a first circuit represented by the instantiation of the first circuit.

Abstract: A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.

Abstract: One aspect of the present disclosure is directed to a metastable ? titanium alloy comprising, in weight percentages: up to 0.05 nitrogen; up to 0.10 carbon; up to 0.015 hydrogen; up to 0.10 iron; greater than 0.20 oxygen; 14.00 to 16.00 molybdenum; titanium; and incidental impurities. Articles of manufacture including the alloy also are disclosed.

Abstract: An austenitic stainless steel composition including relatively low nickel and molybdenum levels, and exhibiting corrosion resistance, resistance to elevated temperature deformation, and formability properties comparable to certain alloys including higher nickel and molybdenum levels. Embodiments of the austenitic stainless steel include, in weight %, up to 0.20 C, 2.0-9.0 Mn, up to 2.0 Si, 16.0-23.0 Cr, 1.0-7.0 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.05-0.35 N, up to 4.0 W, (7.5(% C))?(Nb+Ti+V+Ta+Zr)?1.5, up to 0.01 B, up to 1.0 Co, iron and impurities. Additionally, embodiments of the steel may include 0.5?(Mo+W/2)?5.0 and/or 1.0?(Ni+Co)?8.0.

Abstract: An apparatus includes a telescopic operational amplifier. The telescopic operational amplifier includes an input stage, a load, and a first cascode circuit. The first cascode circuit is coupled to a first differential node and an output node. The first differential node is coupled to one of the input stage and the load. The apparatus includes a first negative transconductance circuit coupled to the first differential node. In at least one embodiment, the first negative transconductance circuit is operable to provide a negative transconductance to compensate at least a first component of an output resistance of the telescopic operational amplifier. In at least one embodiment, the first negative transconductance circuit includes a pair of cross-coupled devices coupled to the first differential node and a current source.

Abstract: An austenitic stainless steel composition including relatively low Ni and Mo levels, and exhibiting corrosion resistance, resistance to elevated temperature deformation, and formability properties comparable to certain alloys including higher Ni and Mo levels. Embodiments of the austenitic stainless steel include, in weight percentages, up to 0.20 C, 2.0-9.0 Mn, up to 2.0 Si, 15.0-23.0 Cr, 1.0-9.5 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.05-0.35 N, (7.5(% C))?(% Nb+% Ti+% V+% Ta+% Zr)?1.5, Fe, and incidental impurities.

Abstract: A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.

Abstract: A method and apparatus are described for generating a display data stream for transmission to a remote display. A display control unit in a processor is configured to multiplex the outputs of a plurality of display controllers to generate a video data stream. A video compression engine (VCE) in the processor receives the video data stream directly from the display control unit without having to go through an external memory or an external display interface. The VCE compresses the video data stream, and optionally encrypts the video data stream. In one embodiment, audio and video data streams may be synchronized into a multiplexed, (and optionally encrypted), audio/video stream before being forwarded for transmission to a remote display. In another embodiment, separate audio and video streams (optionally encrypted) may be forwarded for transmission to the remote display.

Abstract: A method and apparatus are described for processing video data. In one embodiment, a processor is provided with a video compression engine (VCE) that has a memory having a plurality of rows and a plurality of columns of addresses. Video data, (luma data or chroma data), is written in row (i.e., raster) order into the addresses of the memory, and then the data is read out of the addresses in column order. Data is written into the addresses of the columns of the memory as they are read out, which is subsequently read out in row order. This process of switching back and forth between reading and writing data in row and column order continues as the data is read and processed by an encoder to generate a compressed video stream.

Abstract: A supply voltage management system and method for an integrated circuit (IC) die are provided. The supply voltage management system includes one or more temperature sensing elements located on the IC die and configured to sense temperature of the die and to output a sensed temperature value for the die. A dynamic voltage controller is located on the die and is configured to receive the sensed temperature value for the die and to identify a technology process category of the die. Based on the sensed temperature value and the identified technology process category of the die, the dynamic voltage controller adjusts an output voltage to at least one circuit of the die.

Abstract: A memory interface circuit includes a plurality of data bus drivers and logic adapted to be operatively responsive to write driver mask information. If desired, the plurality of bus drivers and the logic may be implemented in separate integrated circuits. The plurality of bus drivers are adapted to be responsive to a write operation. The logic is also adapted to disable any one of the plurality of data bus drivers based on the write driver mask information during the write operation.

Abstract: A thermo-mechanical treatment process is disclosed. A nickel-base alloy workpiece is heated in a first heating step to a temperature greater than the M23C6 carbide solvus temperature of the nickel-base alloy. The nickel-base alloy workpiece is worked in a first working step to a reduction in area of 20% to 70%. The nickel-base alloy workpiece is at a temperature greater than the M23C6 carbide solvus temperature when the first working step begins. The nickel-base alloy workpiece is heated in a second working step to a temperature greater than 1700° F. (926° C.) and less than the M23C6 carbide solvus temperature of the nickel-base alloy. The nickel-base alloy workpiece is not permitted to cool to ambient temperature between completion of the first working step and the beginning of the second heating step. The nickel-base alloy workpiece is worked to a second reduction in area of 20% to 70%. The nickel-base alloy workpiece is at a temperature greater than 1700° F. (926° C.

Abstract: A method and apparatus provides for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

Abstract: An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure.

Abstract: An austenitic stainless steel having low nickel and molybdenum and exhibiting comparable corrosion resistance and formability properties to higher nickel and molybdenum alloys comprises, in weight %, up to 0.20 C, 2.0-9.0 Mn, up to 2.0 Si, 16.0-23.0 Cr, 1.0-5.0 Ni, up to 3.0 Mo, up to 3.0 Cu, 0.1-0.35 N, up to 4.0 W, up to 0.01 B, up to 1.0 Co, iron and impurities, the steel having a ferrite number of less than 10 and a MD30 value of less than 20° C.