Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.
Abstract: A thermal mechanical treatment method includes hot working a precipitation hardening martensitic stainless steel, quenching the stainless steel, and aging the stainless steel. According to certain embodiments, the thermal mechanical treatment does not include solution heat treating the stainless steel prior to aging or cryogenically cooling the stainless steel. An article includes a precipitation hardening martensitic stainless steel having a process history that includes hot working the stainless steel, quenching the stainless steel, and aging the stainless steel. According to certain embodiments, the process history does not include solution heat treating the stainless steel prior to aging or cryogenically cooling the stainless steel.
Abstract: Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.
Type:
Grant
Filed:
July 25, 2008
Date of Patent:
November 20, 2012
Assignee:
ATI Technologies ULC
Inventors:
Neil McLellan, Fei Guo, Daniel Chung, Terence Cheung
Abstract: A method of operating a device is provided. The method includes transitioning the GPU to a substantially disabled state in response to a first received signal, and generating, while the GPU is in the substantially disabled state, a response signal in response to a second received signal. The response signal is substantially similar to a second response signal that would be generated by the GPU in a powered state in response to the second received signal.
Type:
Grant
Filed:
February 26, 2010
Date of Patent:
November 20, 2012
Assignee:
ATI Technologies ULC
Inventors:
Oleksandr Khodorkovsky, Ali Ibrahim, Phil Mummah
Abstract: An apparatus and methods for scheduling and executing commands issued by a first processor, such as a CPU, on a second processor, such as a GPU, are disclosed. In one embodiment, a method of executing processes on a graphics processing unit (GPU) includes monitoring one or more buffers in a memory, selecting a first subset from the one or more buffers for execution on the GPU based on a workload profile of the GPU, and executing the first subset on the GPU. The GPU may also receive a priority ordering of the one or more buffers, where the selecting is further based on the received priority ordering. By performing prioritization and scheduling of commands in the GPU, system performance is enhanced.
Type:
Grant
Filed:
September 3, 2009
Date of Patent:
November 13, 2012
Assignees:
ATI Technologies ULC, Advanced Micro Devices, Inc.
Inventors:
Rex McCrary, Frank Liljeros, Gongxian Jefferey Cheng
Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state.
Abstract: A tool for removing material from a surface includes a body defining a longitudinal bore and an opening connecting an outer surface of the body to the longitudinal bore. A cutting element comprising a cutting surface is dimensioned to be at least partially received by the opening. The cutting surface is configured to translate from a first position to a second position in response to a centrifugal force. In the second position the cutting surface is extended outwardly through the opening, beyond the outer surface of the body. In one example, the tool may be used to remove material, such as oxidation, from the inner walls of a cylindrical article selected from a pipe and a tube.
Abstract: Apparatus and methods provide at least redundant control information such as control symbols and control data over respective channels, such as differential lanes, and skew at least the redundant control information in time between the plurality of transmission circuits. Non-control information such as video and/or audio data may also be skewed. Corresponding receiver circuits and methods are also disclosed.
Abstract: Processes and methods related to producing, processing, and hot working alloy ingots are disclosed. An alloy ingot is formed including an inner ingot core and an outer layer metallurgically bonded to the inner ingot core. The processes and methods are characterized by a reduction in the incidence of surface cracking of the alloy ingot during hot working.
Abstract: A method and apparatus provides pixel information for one or more displays by producing for output on a single link, packet based pixel component multi-stream information on two or more streams. A first stream may include a portion of per-pixel component values, such as RGB pixel component values, whereas the second stream of the multi-stream may include a remaining portion of the per-pixel component values, such as a corresponding alpha value. Hence, multi-streams are employed to communicate, for example, an extended pixel component format for output to one or more displays. The multi-streams are synchronized to provide the pixel component values at a proper time for the receiving display or plurality of displays.
Abstract: A nucleated casting apparatus including an atomizing nozzle configured to produce a droplet spray of a metallic material, a mold configured to receive the droplet spray and form a preform therein, and a gas injector which can limit, and possibly prevent, overspray from accumulating on the mold. The gas injector can be configured to produce a gas flow which can impinge on the droplet spray to redirect at least a portion of the droplet spray away from a side wall of the mold. In various embodiments, the droplet spray may be directed by the atomizing nozzle in a generally downward direction and the gas flow may be directed in a generally upward direction such that the gas flow circumscribes the perimeter of the mold.
Type:
Grant
Filed:
March 15, 2012
Date of Patent:
November 6, 2012
Assignee:
ATI Properties, Inc.
Inventors:
Robin M. Forbes Jones, Sterry A. Shaffer
Abstract: A method of managing resources is provided. The method includes identifying a resource associated with a processor responsive to an impending transition, and copying the identified resource from a memory associated with the GPU or to the memory associated with the GPU.
Type:
Grant
Filed:
January 28, 2010
Date of Patent:
November 6, 2012
Assignees:
Advanced Micro Devices, Inc., ATI Technologies UTC
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
Type:
Grant
Filed:
October 5, 2011
Date of Patent:
November 6, 2012
Assignee:
ATI Technologies ULC
Inventors:
Laurent Lefebvre, Andrew Gruber, Stephen Morein
Abstract: A method to generate super-resolution images using a sequence of low resolution images is disclosed. The method includes generating an estimated high resolution image, motion estimating between the estimated high resolution image and comparison images from the sequence of low resolution images, motion-compensated back projecting, and motion-free back projecting that results in a super resolved image. A corresponding system for generating super-resolution images includes a high resolution image estimation module, a motion estimating module, a motion-compensated back projection module, a motion-free back projection module, an input interface, and an output interface.
Abstract: Various thermal interface structures and methods are disclosed. In one aspect, a method of manufacturing is provided. The method includes providing plural carbon nanotubes in a thermal interface structure. The thermal interface structure is soldered to a side of a semiconductor chip. In another aspect, an apparatus is provided. The apparatus includes a thermal interface structure that has plural carbon nanotubes. A semiconductor chip is soldered to the thermal interface structure.
Type:
Grant
Filed:
June 29, 2009
Date of Patent:
November 6, 2012
Assignees:
Advanced Micro Devices, Inc., ATI Technologies ULC
Abstract: Methods for producing alloy strips including zirconium alloy strips that demonstrate improved formability are disclosed. The strips of the present disclosure have a purity and crystalline microstructure suitable for improved formability, for example, in the manufacture of certain articles such as panels for plate heat exchangers and high performance tower packing components. Other embodiments disclosed herein relate to formed alloy strip, articles of manufacture produced from the alloy strip, and methods for making the articles of manufacture.
Abstract: A system and method for improved antialiasing in video processing is described herein. Embodiments include multiple video processors (VPUs) in a system. Each VPU performs some combination of pixel sampling and pixel center sampling (also referred to as multisampling and supersampling). Each VPU performs sampling on the same pixels or pixel centers, but each VPU creates samples positioned differently from the other VPUs corresponding samples. The VPUs each output frame data that has been multisampled and/or supersampled into a compositor that composites the frame data to produce an antialiased rendered frame. The antialiased rendered frame has an effectively doubled antialiasing factor.
Type:
Application
Filed:
July 2, 2012
Publication date:
November 1, 2012
Applicant:
ATI Technologies, Inc.
Inventors:
Arcot J. PREETHAM, Andrew S. POMIANOWSKI, Raja KODURI
Abstract: A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m?n is disclosed. The method includes forming (m?n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.
Type:
Grant
Filed:
June 3, 2011
Date of Patent:
October 30, 2012
Assignee:
ATI Technologies ULC
Inventors:
Andrew Leung, Roden R. Topacio, Liane Martinez, Yip Seng Low
Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Abstract: Min-axis based mip map determination logic receives a plurality of texture space derivatives with respect to screen space for a given pixel and texel location and selects from a plurality of mip map levels a mip map level based on a min-axis without using a max-axis value and without using an amount of anisotropy. The plurality of mip map levels corresponds to mip map levels of a mip chain. The min-axis may be identified as the squares of the texture space derivatives with respect to either the x-axis or the y-axis of screen space. Selecting the mip map level based on the min-axis ensures that each texel of the selected mip map never maps to more than one pixel during texture mapping where the main texture is of sufficient resolution. Thus, using the mip map level based on the min-axis to fetch texture data from memory and render images results in few aliasing artifacts.