Abstract: A method that decodes serially received MPEG variable length codes by executing instructions in parallel. The method includes an execution unit, which includes multiple pipelined functional units. The functional units execute at least two of the instructions in parallel. The instructions utilize and share general purpose registers. The general purpose registers store information used by at least two of the instructions.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: A robotic tool changer removably attaches a robotic tool to a robotic arm. The changer includes a tool module connected to the robotic tool, and a master module connected to the robotic arm. To attach and detach the robotic tool, the changer couples and uncouples the tool module and the master module. A master electrical signal module (ESM) affixes to the master module and a tool ESM affixes to the tool module. In accordance with design requirements, the changer applies the same power supply to both the master ESM and the tool ESM. The changer, however, selectively suppresses application of the power supply to the tool ESM, while maintaining application of the power supply to the master ESM, during the coupling or uncoupling of the master module and the tool module. In doing so, the changer enables such coupling and uncoupling, while also preventing the formation of transient electric arcs.

Abstract: A method and method and apparatus for data re-arrangement includes the steps of receiving output pixel coordinates (X, Y) and obtaining an input pixel offset value (?S, ?T), wherein the output pixel coordinate represents a location for a two dimensional matrix. The input pixel offset value is obtained in reference to initial input pixel coordinates (S, T) which may be received with the output pixel coordinates or calculated based on the input and/or output pixel coordinates. The input pixel offset value may be any type of representation that provides for a delta value, for example, (?S, ?T) may represent a shift representation for the offset within a matrix array. The method and apparatus for data re-arrangement further includes retrieving an input pixel based on the initial input pixel coordinates and the offset value.

Abstract: A method of integrating a personal computing system and apparatus thereof include processing that begins by integrating a central processing unit with a North bridge on a single substrate such that the central processing unit is directly coupled to the North bridge via an internal bus. The processing then continues by providing memory access requests from the central processing unit to the North bridge at a rate of the central processing unit. The processing continues by having the North bridge buffer the memory access request and subsequently process the memory access requests at a rate of the memory. The method may be expanded by integrating a South bridge onto the same substrate as well as integrating system memory onto the same substrate.

Abstract: According to the present disclosure, a transmitter for transmitting control characters to a display device over an interface includes a transmitter portion configured to transmit a control character having a plurality of bit values to the display device. The transmitter also includes logic configured to determine values of the bits in the control character and construct a corresponding plurality of rebalancing control characters based on the determination of the values of the plurality of bits in the control character to have bit values selected such that the combination of the control character and rebalancing control character is DC balanced. As such, the transmitter provides DC balance correction to non-DC balanced control characters in such a way as to allow DVI and HDMI to operate properly on an AC-coupled connection.

Abstract: Embodiments of a method and apparatus for using graphics memory (also referred to as video memory) for non-graphics related tasks are disclosed herein. In an embodiment a graphics processing unit (GPU) includes a VRAM cache module with hardware and software to provide and manage additional cache resourced for a central processing unit (CPU). In an embodiment, the VRAM cache module includes a VRAM cache driver that registers with the CPU, accepts read requests from the CPU, and uses the VRAM cache to service the requests. In various embodiments, the VRAM cache is configurable to be the only GPU cache or alternatively, to be a first level cache, second level cache, etc.

Abstract: The present invention provides a method and apparatus for data compression that includes representing each sub-pixel of each pixel with a pointer corresponding to an attribute of the sub-pixel, the attribute being a floating point binary number. An overall attribute of each pixel is then determined. The determining of the overall attribute of each tile may include any one of assigning the attribute of the sub-pixels to the overall attribute of the pixel when the sub-pixels are represented by an identical pointer, and resolving the overall attribute of the tile by the attributes of the sub-pixels when the sub-pixels are represented by non-identical pointers of the pixel.

Abstract: In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an interconnect between the components and constructing transaction units which are sent over the interconnect to initiate memory access operations. The approach may also be used to allow for a degree of communication between device components.

Abstract: A circuit includes a clock generator for providing a clock signal to a synchronously operated digital circuit and a control signal generator for providing a control signal to the synchronously operated digital circuit. The control signal generator is interconnected to the clock generator to suppress the clock signal for a defined duration as a control signal is provided. The defined duration allows the control signal to settle to allow said synchronously operated digital circuit to unambiguously sample said control signal. The control signal generator may place the synchronous digital circuit in a lower power consumption state.

Abstract: A thermal management device for a circuit substrate having at least a first heat generating component and at least a second heat generating component, the thermal management device includes a first thermal spreader and a second thermal spreader. The second thermal spreader is mountable to the circuit substrate to thermally couple with the second heat generating component. Additionally, the second thermal spreader is adapted to couple to the first thermal spreader to thermally couple the first thermal spreader to the first heat generating component when the second thermal spreader is mounted to the circuit substrate. The thermal management device also includes a bias device that is coupled to the first thermal spreader and the second thermal spreader and is adapted to maintain the thermal coupling between the first thermal spreader and the first heat generating component when the second thermal spreader is mounted to the circuit substrate.

Abstract: A circuit includes an input/output buffer circuit. The input/output buffer circuit includes an output buffer circuit and a bias control circuit. The output buffer circuit provides an output voltage in response to output information. The bias control circuit provides an output buffer bias voltage based on the output voltage.

Abstract: A method and apparatus for detecting semi-transparencies in video is disclosed.

Abstract: A graphics processing system comprises a command processing engine capable of processing pixel command threads and vertex command threads. The command processing engine is coupled to both a renderer and a scan converter. Upon completing processing of a command thread, which may comprise a pixel command thread or a vertex command thread, the command engine provides the command thread to either the renderer or the scan converter.

Abstract: A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information.

Abstract: Coherent memory copy logic is operative to copy data from a source memory location to a destination memory location and duplicate a write request to a source memory region to produce a duplicated write request. Coherent memory copy logic is also operative to execute the duplicated write request to copy content from the external memory region to the destination memory region. Power to the source memory can then be reduced to save power while the internal memory is being used. Accordingly, a type of “hardware memory mover” does not require the use of any complex software synchronization and does not result in any service interruption during a memory move. The coherent memory copy logic reallocates the application memory space from, for example, external memory to internal memory within a chip in a manner that is transparent to the application software and the user. Corresponding methods are also set forth.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A method includes generating a first, second and third voltage output from a temperature sensing element of an integrated circuit using a respective, corresponding first, second and third, switched current source, for sequentially switching a respective first, second and third excitation current through the temperature sensing element, wherein the third switched current source generates the corresponding third voltage output as a reference voltage between the first voltage and the second voltage; and calculating an error corrected difference between the first voltage and the second voltage using the reference voltage. In the method, the second excitation current is proportional to the first excitation current by a value n, and the third excitation current is proportional to the first excitation current by the square root of n.

Abstract: An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a command thread from either the plurality of pixel or vertex command threads based on relative priorities of the plurality of pixel command threads and the plurality of vertex command threads. The selected command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.