Abstract: A monitoring device and method are provided to monitor a separate device for malfunctions and to control and restore the malfunctioning monitored device to a normal functioning state. A malfunction state includes the monitored device being powered off or in a standby power state. The monitoring device includes control logic operative to determine a malfunction state of the monitored device and to control a reapplication of power to the monitored device to reboot the monitored device based on the determined malfunction state of the monitored device. The method for monitoring and controlling the monitored device comprises the steps of: determining a malfunction state of the monitored device; and controlling a reapplication of power to the monitored device to reboot the monitored device based on the determined malfunction state of the monitored device.

Abstract: A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).

Abstract: Methods and apparatus for producing large diameter superalloy ingots are disclosed. A material comprising at least one of a metal and a metallic alloy is introduced into a pressure-regulated chamber in a melting assembly. The material is subjected to a wide-area electron field within the pressure-regulated chamber to heat the material to a temperature above the melting temperature of the material to form a molten alloy. At least one stream of molten alloy from the pressure-regulated chamber is provided from the melting assembly and is fed into an atomizing assembly, where particles of the molten alloy are generated by impinging electrons on the molten alloy to atomize the molten alloy. At least one of an electrostatic field and an electromagnetic field are produced to influence the particles of the molten alloy. The particles of the molten alloy are deposited onto a collector in a spray forming operation to form an alloy ingot.

Abstract: Methods and apparatus for translating messages in a computing system are disclosed. In particular, a disclosed method for converting messages in a computer system includes receiving a command message from a processing unit where the message is defined according to a transport protocol that utilizes command messages using an address to communicate commands to devices in the computer system. The command message is translated to an interface standard by mapping the address into an address field of a packet constructed according to the interface standard. Corresponding apparatus that perform the methods are also disclosed.

Abstract: One non-limiting embodiment of an apparatus for forming an alloy powder or preform includes a melting assembly, an atomizing assembly, and a collector. The melting assembly produces at least one of a stream of a molten alloy and a series of droplets of a molten alloy, and may be substantially free from ceramic in regions contacted by the molten alloy. The atomizing assembly generates electrons and impinges the electrons on molten alloy from the melting assembly, thereby producing molten alloy particles.

Abstract: A nucleated casting apparatus including an atomizing nozzle configured to produce a droplet spray of a metallic material, a mold configured to receive the droplet spray and form a preform therein, and a gas injector which can limit, and possibly prevent, overspray from accumulating on the mold. The gas injector can be configured to produce a gas flow which can impinge on the droplet spray to redirect at least a portion of the droplet spray away from a side wall of the mold. In various embodiments, the droplet spray may be directed by the atomizing nozzle in a generally downward direction and the gas flow may be directed in a generally upward direction such that the gas flow circumscribes the perimeter of the mold.

Abstract: Apparatus and methods are disclosed for controlling the memory controller and, in particular, controlling signaling of the memory controller to a memory via memory interface during a static screen condition. An apparatus includes static image detection logic that is configured to detect when image data being displayed by a display controller is static and to communication detection of static image data to the display controller. The apparatus also includes control logic within the display controller responsive to the static image detection logic, where the control logic is configured to detect a level of a line buffer within the display controller and to send a signal to a memory controller directing the memory controller to issue a signal to a memory to enter a self-refresh mode, thereby turning off at least one memory clocking circuit within the memory controller. A corresponding method is also disclosed.

Abstract: A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like.

Abstract: A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Abstract: An image processing circuit, such as a graphics accelerator chip or any other suitable circuit, includes display output control logic that is operative to receive a current frame of information from a frame buffer and is operative to process a current frame, such as by providing gamma correction, image scaling, graphics or video overlaying, or other suitable processing, to produce a processed current display frame and stores the processed current display frame back in the frame buffer. Fixed function or dedicated, display type specific temporal processing logic receives the processed current display frame stored in the frame buffer and also obtains at least one previous processed current display frame from the frame buffer and temporally processes pixels from each of the processed current display frame and the previous processed current display frame to produce a temporally compensated display frame for a specific type of display.

Abstract: The present invention is a unified shader unit used in texture processing in graphics processing device. Unlike the conventional method of using one shader for texture coordinate shading and another for color shading, the present shader performs both operations. The unified shader uses the same precision for both texture coordinate and color shading, thus simplifying the complexity of programming for two separate conventional shaders with different levels of precision. Furthermore, the present invention uses enhanced scheduling logic to perform indirect texture and bump mapping in a single first-in, first-out (FIFO) memory structure and avoids the problems associated with large FIFOs with buffer registers found in conventional shaders. In one embodiment, a plurality of ALU-memory pairs are synchronized to form a plurality of pipelines to execution shading instructions. In another embodiment, a plurality of unified shaders are synchronized and connected together to processing shading operations concurrently.

Abstract: A method and apparatus for reducing motion judder in a 3D input source are disclosed. The 3D input source is separated into left and right images. Motion vectors for the left and right images are calculated. Frame rate conversion is performed on the left and right images, to produce motion compensated left and right images. The left and right images and the motion compensated left and right images are reordered for display. Alternatively, the motion estimation and motion compensation can be performed on the 3D input source, and the input image and the motion compensated image can then be separated into respective left and right images. The method and apparatus can be adapted to perform 2D to 3D conversion by extracting a 2D input source into left and right 3D images and performing motion estimation and motion compensation.

Abstract: An image noise filter includes a wavelet transform module and an edge based adaptive filter module. The dual tree wavelet transform module provides low frequency wavelet information and high frequency wavelet information in response to image information. The edge based adaptive filter module provides filtered high frequency wavelet information in response to the high frequency wavelet information and edge information that is based on the low frequency wavelet information.

Abstract: Various semiconductor chip passivation structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a polymeric passivation layer to a side of a semiconductor chip. The side of the semiconductor chip includes plural conductor pads. Plural openings are formed in the polymeric passivation layer to expose the plural conductor pads. Plural conductor structures are formed on the plural conductor pads.

Abstract: A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

Abstract: The present disclosure discusses methods and apparatus for controlling the video playback in a video playback system. In particular, a method for controlling video playback includes receiving a flip call to display video data from a flip queue buffer. Processing of the video data is then initiated. Flip acknowledgement information is issued in response to receiving the flip call information and prior to completion of the processing of video data to be displayed from the flip queue buffer. By issuing flip acknowledgement information regardless of whether the processing of the video data has been completed, video flip calls can continue to be issued at a constant rate and other processing can continue without waiting, thus resulting in better and smoother video playback and economizing processing resources. Additionally, a decision whether or not to drop a particular video frame is made based on whether a flip queue buffer from a predetermined number of flip queue buffers is available.

Abstract: An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation.

Abstract: A method and apparatus for combining video graphics processing and audio processing onto the same single chip and/or printed circuit board includes a graphics processing circuit, an audio processing circuit, a local bus, and a bus arbitrator. The local bus couples both the graphics processing circuit and audio processing circuit to the system bus such that each of the circuits may transceive data with the system bus. The bus arbitrator arbitrates access to the local bus between the graphics processing circuit and audio processing circuit. Such arbitration is based on incoming data, which is interpreted and, based on the interpretation, the bus arbitrator routes the incoming data to either the graphics processing circuit or the audio processing circuit. In addition, the bus arbitrator arbitrates outputting data from the graphics processing circuit and the audio processing circuit based on commands received from the CPU.

Abstract: An automatic transmission line pressure regulator includes a first body for installation in a valve bore distant from a line pressure valve and having a threaded bore passing therethrough, a threaded adjuster axially engaged in the threaded bore and rotationally adjustable with respect to the first body, a second body for installation in the valve bore and engagement with the threaded adjuster and a spring for installation between and engagement with the second body and the line pressure valve. Rotation of the threaded adjuster with respect to the first body alters an axial position of the adjuster, the second body and a first end of the spring, thereby altering a pre-load on the spring to alter a resistive force against movement of the line pressure valve caused by line pressure, and thusly, regulates line pressure.

Abstract: A quick disconnect tooling apparatus for releasably latching an end effector tool to a manipulator. The present invention provides a base module connectable to a manipulator, and a tool module connectable to the end effector tool. A power source coupling has a first portion coupled to the base module, and a second portion coupled to the tool module, wherein the first and second portions of the power source coupling may cooperatively engage one another to allow for the passing of power between the manipulator and the end effector tool.