Abstract: A method of signal processing according to an embodiment includes estimating a response of a transmission channel during a symbol period. Based on an estimated response of the transmission channel, components of a model of a phase noise process during the symbol period are estimated. Based on the phase noise process model, an estimate of a symbol received during the symbol period is obtained.

Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter (DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the color being viewed on the screen is uniform regardless of which VGA is providing the signal. When a VGA is not providing information to the output port, a dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port.

Abstract: A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics aperture relocation table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. Thus, unique addresses need not be generated for each VPU.

Abstract: A power up biasing circuit for a split power supply based circuit includes a split power supply state sensing circuit that produces a pair of complimentary control signals indicating a presence or absence of a suitable biasing power supply voltage. A pseudo power supply voltage, based on a first power supply is selected by a selector circuit for acting as a biasing voltage for one or a plurality of components to be protected during initial power up where there is an absence of a second power supply voltage, based on the pair of complimentary control signals. Once the second power supply voltage has fully ramped up to steady state, the selector circuit selects the second power supply voltage as the biasing voltage for one or a plurality of component to be protected.

Abstract: Systems, methods, and apparatus for noise reduction include noise estimation from blanking interval information. Such systems, methods, and apparatus may also include temporal filtering, scene change detection, inverse telecine, and/or DC preservation.

Abstract: A method and system for accommodating at least one high priority data element from a plurality of data elements written into a ring buffer including a processor that preempts a ring buffer by modifying at least one of the data elements previously written to the ring buffer to create modified data elements in response to detecting a high priority data element to be written into the ring buffer. The processor modifies the plurality of data elements previously written to the ring buffer to create the modified data elements. The processor resubmits to the ring buffer at least one of the data elements corresponding to at least one of the modified data elements for execution by a graphics co-processor in response to processing the at least one high priority data element.

Abstract: Provided are systems, methods, and computer program products for integrating external input into an application, with little or no modification to the application. Such a system includes a graphics processing unit (GPU) and an interface module. The GPU is configured to execute graphics processing tasks for the application. The interface module is configured to (i) receive a camera view of the application and an input from an after-market device and (ii) generate an adjusted camera view based on the camera view of the application and the input from the after-market device. The adjusted camera view is then provided to a display device.

Abstract: A method for determining the appearance of a pixel includes receiving fragment data for a pixel to be rendered; storing the fragment data; and determining an appearance value for the pixel based on the stored fragment data, wherein a portion of the stored fragment data is dropped when the number of fragment data per pixel exceeds a threshold value enabling large savings in memory footprint without impacting perceivably on the image quality. A graphics processor includes a rasterizer operative to generate fragment data for a pixel to be rendered in response to primitive information; and a render back end circuit, coupled to the rasterizer, operative to determine a pixel appearance value based on the fragment data by dropping the fragment data having the least effect on pixel appearance.

Abstract: A graphics processing circuit includes an anti-aliasing and stippling circuit operative to provide a primitive texture coordinate set in response to vertex data, the anti-aliasing and stippling circuit performing anti-aliasing operations, in parallel, with at least one appearance attribute determination operation on the vertex data, a rasterizer, coupled to the anti-aliasing and stippling circuit, operative to generate a pixel texture coordinate set in response to the primitive texture coordinate set, and apply an appearance value to a pixel defined by the pixel texture coordinate set, and a texture circuit, coupled to the rasterizer, operative to retrieve the appearance value from a corresponding one of a plurality of textures in a multi-texture map in response to the pixel texture coordinate set, the multi-texture map including data representing point, line and polygon texture data.

Abstract: The present application discloses a method for communicating between at least two different levels of software components. The method includes establishing a command set common to the at least two different levels of software components. Additionally, the method includes providing a command decoder operable by both of the at least two levels of software components, the command decoder configured to decode the command set. By providing a common command set between different levels of software components, such as a software driver and a BIOS, where the commands within the command table are interpreted and executed by an identical command decoder that interprets and executes the same command tables, this ensures that the same features or functions are implemented or executed in the same way across different levels of the software components. Accordingly, redundant implementation of the same functions by different software components is eliminated.

Abstract: The present disclosure relates to methods and apparatus for controlling power consumption of a plug-in card or circuit module. The disclosed method, in particular, controls power to a circuit module and includes implementing a user interface and power manager to automatically control the power state of the circuit module by, among other things, powering the module up or down using a simulated hot unplug of the device. The apparatus further includes use of an I/O interconnect to allow the system BIOS to simulate the hot unplugging of the module.

Abstract: A thermal mechanical treatment method includes hot working a precipitation hardening martensitic stainless steel, quenching the stainless steel, and aging the stainless steel. According to certain embodiments, the thermal mechanical treatment does not include solution heat treating the stainless steel prior to aging or cryogenically cooling the stainless steel. An article includes a precipitation hardening martensitic stainless steel having a process history that includes hot working the stainless steel, quenching the stainless steel, and aging the stainless steel. According to certain embodiments, the process history does not include solution heat treating the stainless steel prior to aging or cryogenically cooling the stainless steel.

Abstract: A disclosed method comprises obtaining location data including geographic coordinates; searching stored digital video broadcast network requirements data corresponding to the location data; and tuning to a digital video broadcast network channel indicated by the digital video broadcast network requirements data. The step of obtaining location data may further comprise obtaining Global Positioning System (GPS) data; and searching using the GPS data. An integrated circuit includes tuner logic, operative to tune to, and receive, a digital video broadcast network channel in response to a command; location data logic to receive location data; digital video broadcast network reception requirements logic to obtain location data from the location data logic and search stored digital video broadcast network requirements data corresponding to the location data, and send the command to the tuner logic to tune to a digital video broadcast network channel indicated by the digital video broadcast network requirements data.

Abstract: Methods for producing zirconium strips that demonstrate improved formability are disclosed. The zirconium strips of the present disclosure have a purity and crystalline microstructure suitable for improved formability, for example, in the manufacture of certain articles such as panels for plate heat exchangers and high performance tower packing components. Other embodiments disclosed herein relate to formed substantially pure zirconium strip, articles of manufacture produced from the substantially pure zirconium strip, and methods for making the articles of manufacture.

Abstract: A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages.

Abstract: A system includes a processing device, at least one data processing module, and a security control module. The security control module is operatively connected to both the processing device and the data processing module. The security control module is operative to control access to a protected register that is associated with the at least one data processing module. As such, the security control module operates as a firewall or filter to allow or deny access to a protected register. Security-unaware data processing module are therefore secured in the system at a central location while eliminating the need to use only security-aware data processing module. A method for securing data processing modules, including security-unaware data processing module, is also disclosed.

Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.

Abstract: A circuit includes a circuit identification storage module and a control module. The circuit identification storage module stores circuit identification information. The control module receives the circuit identification information and in response thereto selectively performs a secure boot procedure or a test boot procedure. The control circuit performs the secure boot procedure when the circuit identification information indicates that the circuit is a production circuit. The control circuit performs the test boot procedure when the circuit identification information indicates that the circuit is a test circuit. A related method is also disclosed.

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an interlink module is coupled to receive processed data corresponding to the frames from each of the multiple processors. The interlink module selects pixels of the frames from the processed data of one of the processors based on a predetermined pixel characteristic and outputs the frames that include the selected pixels.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.