Patents Assigned to Atrenta Inc.
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Publication number: 20150379186Abstract: A method implemented as a test grading system (TGS) in a programmable computing system grades simulation tests according to their verification property coverage. The TGS identifies verification properties from one or more of the circuit design (e.g. RTL description), verification properties files and test simulation results, and determines verification property coverage for each test. That is, it finds out which verification properties are covered by each simulation test. According to a specified criterion, the TGS recommends a subset of the available tests based on their verification property coverage.Type: ApplicationFiled: June 22, 2015Publication date: December 31, 2015Applicant: ATRENTA, INC.Inventors: Yong Liu, Jian Yang, Yuan Lu
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Publication number: 20150379176Abstract: A configurable module editor and viewer (CMVE) reads the RTL description of a configurable module keeping track of all possible configuration options. Configuration options include pre-processor macros that are normally removed by RTL parsers. The CMVE allows users to view multiple configurations simultaneously. The CMVE assists users in editing the configurable module by presenting a simplified view of interest, while automatically propagating changes and maintaining consistency in the configurable module. The CMVE outputs updated RTL that maintains all configuration options.Type: ApplicationFiled: June 22, 2015Publication date: December 31, 2015Applicant: ATRENTA, INC.Inventors: Anshuman Nayak, Samantak Chakrabarti, Nilam Sachan, Nitin Bhardwaj, Brijesh Agrawal, Nishant Sharma
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Publication number: 20150356222Abstract: A system and methods provide for an analysis of at least a portion of an integrated circuit (IC) that comprises a plurality of modules, for the purpose of identifying signals that can be indicative of the activity of the modules. By analyzing the activity of these signal immediately before and immediately after each module going from non-idle to idle and from idle to non-idle respectively, it is possible to determine which signals provide an indication that the module should be shut down. If the module can be shut down in idle state, then these input signals may be used as control signals for this purpose. By reporting to a designer the role of such signals a simple design change for detecting the activity and controlling the module, can save on power consumption, in ways not previously detected by the designer.Type: ApplicationFiled: January 20, 2015Publication date: December 10, 2015Applicant: ATRENTA, INC.Inventors: Solaiman Rahim, Sean Safarpour, Shekaripuram V. Venkatesh, Siddharth Guha, Fahim Rahim
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Patent number: 9135382Abstract: Systems and methods for functionally verifying the performance of a system on a chip (SOC) are provided herein. According to some embodiments, the methods may include at least the steps of analyzing a verification log, via a functional verification system, to determine signatures by correlating a pattern of at least one of triggered and untriggered assertions in one or more blocks of a plurality of blocks to behaviors of at least one of the SOC and the one or more blocks of the plurality of blocks. Exemplary methods also include categorizing signatures according to the behaviors, and storing similar signatures based upon the categorization in a database.Type: GrantFiled: November 8, 2012Date of Patent: September 15, 2015Assignee: Atrenta, Inc.Inventors: Yuan Lu, Nitin Mhaske, Yunshan Zhu
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Publication number: 20150234959Abstract: A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: ATRENTA, INC.Inventors: Sridhar Gangadharan, Barsneya Chakrabarti, Manish Goel, Mohammad H. Movahed-Ezazi
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Publication number: 20150143307Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.Type: ApplicationFiled: March 4, 2014Publication date: May 21, 2015Applicant: ATRENTA, INC.Inventors: Solaiman Rahim, Mohammad H. Movahed-Ezazi
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Patent number: 8984457Abstract: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage.Type: GrantFiled: April 16, 2013Date of Patent: March 17, 2015Assignee: Atrenta, Inc.Inventors: Mohamed Shaker Sarwary, Maher Mneimneh, Mohammad H. Movahed-Ezazi
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Patent number: 8984469Abstract: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.Type: GrantFiled: December 13, 2013Date of Patent: March 17, 2015Assignee: Atrenta, Inc.Inventors: Solaiman Rahim, Mohammad H. Movahed-Ezazi, Siddharth Guha, Vaibhav Jain
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Patent number: 8930863Abstract: Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup, and move operations to efficiently and optimally implement the desired hierarchy modifications. Any modifications to port and signal names are automatically resolved by the system and the resultant RTL matches the function of the input RTL. The user then evaluates the revised hierarchy with regard to power distribution and routing congestion, and further hierarchy modifications are performed if necessary. A widget user interface facility is included to allow user-guided direction of hierarchy modifications in an iterative fashion.Type: GrantFiled: March 14, 2013Date of Patent: January 6, 2015Assignee: Atrenta, Inc.Inventors: Anshuman Nayak, Samantak Chakrabarti, Brijesh Agrawal, Nilam Sachan
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Patent number: 8881075Abstract: An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.Type: GrantFiled: March 4, 2013Date of Patent: November 4, 2014Assignee: Atrenta, Inc.Inventors: Yuan Lu, Yong Liu, Nitin Mhaske
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Patent number: 8863058Abstract: A method for timing optimization of an integrated circuit design using a timing optimization system comprising loading an original delay value and an original gate configuration net-list for an original gate from a results database. A near optimum gate configuration is identified using near optimum gate configuration information stored in a delay characterization database for the original gate. A near optimum delay value and a near optimum gate configuration net-list of a near optimum gate configuration are loaded. A timing optimized gate configuration is provided from running an incremental static timing analysis of the near optimum gate configuration.Type: GrantFiled: September 24, 2012Date of Patent: October 14, 2014Assignee: Atrenta, Inc.Inventors: Anup Nagrath, Sanjiv Mathur
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Patent number: 8856706Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.Type: GrantFiled: May 6, 2013Date of Patent: October 7, 2014Assignee: Atrenta, Inc.Inventors: Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
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Publication number: 20140298281Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.Type: ApplicationFiled: October 16, 2013Publication date: October 2, 2014Applicant: Atrenta, Inc.Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
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Publication number: 20140282338Abstract: Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup, and move operations to efficiently and optimally implement the desired hierarchy modifications. Any modifications to port and signal names are automatically resolved by the system and the resultant RTL matches the function of the input RTL. The user then evaluates the revised hierarchy with regard to power distribution and routing congestion, and further hierarchy modifications are performed if necessary. A widget user interface facility is included to allow user-guided direction of hierarchy modifications in an iterative fashion.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: ATRENTA, INC.Inventors: Anshuman Nayak, Samantak Chakrabarti, Brijesh Agrawal, Nilam Sachan
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Publication number: 20140282322Abstract: A system and method identify potentially static and/or quasi-static signals within an integrated circuit (IC), or portion thereof. Static and quasi-static signals may be identified in a design description of the IC by any one or more of: (1) a fan-out size exceeding some threshold, (2) a toggle frequency in a simulation trace that is below some threshold, and (3) a signal name that appears in a list accessed from the memory. Identification of static and quasi-static signals is performed, typically, as part of a verification process in order to flag cases where the verification system would otherwise indicate an error (e.g., at a clock domain crossing). Identifying a signal of the IC as being static or quasi-static improves the quality of results of verification and makes it easier for a prospective user to concentrate on actual rather than spurious issues reported during verification.Type: ApplicationFiled: April 29, 2013Publication date: September 18, 2014Applicant: Atrenta, Inc.Inventors: Mohamed Shaker Sarwary, Maher Mneimneh, Paras Mal Jain, Mohammad H. Movahed-Ezazi, Jean P. Binois
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Publication number: 20140282347Abstract: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.Type: ApplicationFiled: December 13, 2013Publication date: September 18, 2014Applicant: Atrenta, Inc.Inventors: Solaiman Rahim, Mohammad H. Movahed-Ezazi, Siddharth Guha, Vaibhav Jain
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Publication number: 20140282321Abstract: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage.Type: ApplicationFiled: April 16, 2013Publication date: September 18, 2014Applicant: Atrenta, Inc.Inventors: Mohamed Shaker Sarwary, Maher Mneimneh, Mohammad H. Movahed-Ezazi
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Patent number: 8839171Abstract: System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files.Type: GrantFiled: October 16, 2013Date of Patent: September 16, 2014Assignee: Atrenta, Inc.Inventors: Ravi Varadarajan, Jitendra Gupta, Sanjiv Mathur, Priyank Mittal, Kaushal Kishore Pathak, Kshitiz Krishna, Anup Nagrath, Ritesh Mittal
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Publication number: 20140250414Abstract: An assertion-based verification tool for circuit designs includes an effective measurement of assertion density for any given generated set of assertions. A register-transfer level (RTL) description of an integrated circuit (IC) is used to compute a set of predicates. Then, determination is made as to the number of predicates that are satisfiable on the given set of assertions received respective of the RTL description. Thereafter, simulation traces for the RTL are received and the number of predicates satisfiable on the simulation traces is computed. A figure of merit of assertion density is determined from the ratio of the respective numbers of predicates. The set of assertions may be modified as required to satisfy a predetermined threshold value of assertion density, to assure that a circuit is rigorously tested by the verification tool.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: Atrenta, Inc.Inventors: Yuan Lu, Yong Liu, Nitin Mhaske
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Patent number: 8813003Abstract: A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.Type: GrantFiled: October 17, 2013Date of Patent: August 19, 2014Assignee: Atrenta, Inc.Inventors: Anshuman Nayak, Samantak Chakrabarti, Brijesh Agrawal, Nitin Bhardwaj