Abstract: Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.

Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.

Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.

Abstract: Level shifter modules, used in integrated circuits (ICs), are automatically inserter and their correctness verified. A level shifter module for signals crossing voltage domains is generated, and instances thereof are inserted in a pre-determined voltage domain. Several checks ensure the correctness of the inserted level shifter module. The level shifter modules are instantiated based on user-defined voltage constraints.

Abstract: A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.

Abstract: A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be found much later in the design or manufacturing cycle.

Abstract: A method for evaluating the upper bound fault coverage of an integrated circuit (IC) or a portion thereof from register transfer level (RTL) description is provided. The method requires the analysis of a circuit described in RTL consisting of primary input and output pins as well as devices connected to each other and/or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘stuck at zero’ and ‘stuck at one’ conditions. The upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit. The method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources.

Abstract: A method for evaluating the upper bound fault coverage of an integrated circuit (IC) or a portion thereof from register transfer level (RTL) description is provided. The method requires the analysis of a circuit described in RTL consisting of primary input and output pins as well as devices connected to each other and/or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘stuck at zero’ and ‘stuck at one’ conditions. The upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit. The method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources.

Abstract: A method for efficiently detecting bus contention from a register transfer level (RTL) description is provided. A bus contention occurs if more than two components try to propagate data onto a bus at the same time. The provided method simulates possible input combinations and detects whether there is a possibility for a bus contention. In addition, the provided method is designed for testability, therefore using the method, the designer may identify contention that may exist in test mode at the RTL level of the design even when such conditions may not occur in system mode. The method provides the designer with the input combination as well as the RTL statement that caused the contention. The method detects the bus contention by simulating a small number of input combinations.

Abstract: A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream implementation of that device to expose potential implementation problems that would otherwise be found much later in the design or manufacturing cycle.