Patents Assigned to Atrenta Inc.
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Patent number: 8589835Abstract: A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.Type: GrantFiled: March 29, 2012Date of Patent: November 19, 2013Assignee: Atrenta, Inc.Inventors: Anshuman Nayak, Samantak Chakrabarti, Brijesh Agrawal, Nitin Bhardwaj
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Publication number: 20130290917Abstract: A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design.Type: ApplicationFiled: June 25, 2012Publication date: October 31, 2013Applicant: ATRENTA, INCInventors: Anshuman NAYAK, Samantak CHAKRABARTI, Brijesh AGRAWAL, Nitin BHARDWAJ
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Patent number: 8560988Abstract: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.Type: GrantFiled: August 15, 2011Date of Patent: October 15, 2013Assignee: Atrenta, Inc.Inventor: Mohamed Shaker Sarwary
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Publication number: 20130246989Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Atrenta, IncInventors: Maher MNEIMNEH, Shaker SARWARY, Paras Mal JAIN, Ashish BANSAL, Mohammad MOVAHED-EZAZI, Namit GUPTA
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Publication number: 20130239080Abstract: Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: ATRENTA, INC.Inventors: Mohamed Shaker SARWARY, Maher MNEIMNEH, Paras Mal JAIN, Deepak AHUJA, Mohammad Homayoun MOVAHED-EZAZI
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Patent number: 8533647Abstract: In order to realize some of the advantages described above, there is provided a computer-implemented method for verification of an intellectual property (IP) core in a system-on-chip (SoC). The method comprises generating a plurality of verification specific abstracted views of the IP core each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.Type: GrantFiled: October 5, 2012Date of Patent: September 10, 2013Assignee: Atrenta, Inc.Inventors: Sridhar Gangadharan, Mohammad H. Movahed-Ezazi, Shaker Sarwary, Fadi Maamari, Subir Subir Ray
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Publication number: 20130212545Abstract: Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing is keeping the power dissipation during testing under the allowed power capabilities of the tester power supplies, as the power used during scan test is much higher than that used during functional testing. A method for estimating the power dissipation of scan blocks in a circuit during the design stage is disclosed. Using the results generated, the circuit designer divides the design into an optimum number of scan blocks for test. Thus at-speed scan of the individual or groups of scan blocks can be estimated, during design, for optimizing test time while keeping the test power within acceptable limits.Type: ApplicationFiled: March 20, 2013Publication date: August 15, 2013Applicant: Atrenta, Inc.Inventor: Atrenta, Inc
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Publication number: 20130185682Abstract: A system and methods are disclosed for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs. In particular, rule-based interface matching is automatically performed by analyzing actual port names on instances of functional elements and blocks to form signal groupings that comprise a higher-level abstracted description. An example syntax is provided for defining rules that are used to define how various analysis are performed. Data describing standard interfaces on common Intellectual Property (IP) blocks is optionally made available to facilitate interface matching. Also, a facility is included to allow user-guided mapping on instantiated interfaces with respect to actual port names in an RTL-level design.Type: ApplicationFiled: March 29, 2012Publication date: July 18, 2013Applicant: ATRENTA, INCInventors: Anshuman NAYAK, Samantak CHAKRABARTI, Brijesh AGRAWAL, Nitin Bhardwaj
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Patent number: 8448111Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.Type: GrantFiled: January 7, 2011Date of Patent: May 21, 2013Assignee: Atrenta, Inc.Inventors: Maher Mneimneh, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
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Patent number: 8423843Abstract: Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing is keeping the power dissipation during testing under the allowed power capabilities of the tester power supplies, as the power used during scan test is much higher than that used during functional testing. A method for estimating the power dissipation of scan blocks in a circuit during the design stage is disclosed. Using the results generated, the circuit designer divides the design into an optimum number of scan blocks for test. Thus at-speed scan of the individual or groups of scan blocks can be estimated, during design, for optimizing test time while keeping the test power within acceptable limits.Type: GrantFiled: October 22, 2010Date of Patent: April 16, 2013Assignee: Atrenta, Inc.Inventor: David Allen
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Publication number: 20130014068Abstract: In the field of integrated circuit (IC) design it is common to use a plurality of design constraints files to provide the appropriate operational mode when checking the design. Designers typically use the Synopsis® design constraint (SDC) format to describe the constraints in each operational mode. Each time an operational mode is tested a corresponding SDC is used. By merging a plurality of SDCs into a single most pessimistic SDC, designers are able to ensure that the device will properly operate in all the defined operational modes. Only a single run of the merged SDC in the hypothetical mode is required thereby saving time as well as avoiding potential errors from conflicting constraints in different operational modes.Type: ApplicationFiled: July 8, 2011Publication date: January 10, 2013Applicant: ATRENTA, INC.Inventors: Sridhar GANGADHARAN, Manish GOEL, Amit HANDA
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Patent number: 8285527Abstract: As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating changes the state function it is necessary to perform a sequential equivalence checking (SEC) verification. Applying a full SEC may be runtime consuming and is not scalable for large designs. Methods to reduce the problem of verifying sequential clock gating by reducing the sequential problem into much smaller problem that can be easily solved is therefore shown.Type: GrantFiled: May 24, 2010Date of Patent: October 9, 2012Assignee: Atrenta, Inc.Inventors: Solaiman Rahim, Pradeep Kumar Nalla
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Publication number: 20120180015Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.Type: ApplicationFiled: January 7, 2011Publication date: July 12, 2012Applicant: ATRENTA, INC.Inventors: Maher MNEIMNEH, Shaker Sarwary, Paras Mal Jain, Ashish Bansal, Mohammad Movahed-Ezazi, Namit Gupta
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Publication number: 20120042294Abstract: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.Type: ApplicationFiled: August 15, 2011Publication date: February 16, 2012Applicant: ATRENTA, INC.Inventor: Mohamed Shaker SARWARY
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Publication number: 20110288825Abstract: As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating changes the state function it is necessary to perform a sequential equivalence checking (SEC) verification. Applying a full SEC may be runtime consuming and is not scalable for large designs. Methods to reduce the problem of verifying sequential clock gating by reducing the sequential problem into much smaller problem that can be easily solved is therefore shown.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Applicant: ATRENTA, INC.Inventors: Solaiman RAHIM, Pradeep Kumar NALLA
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Patent number: 8042085Abstract: A technique and apparatus for reducing the complexity of optimizing the performance of a designed semiconductor circuit is disclosed. This technique of path compaction is used to reduce the time taken for optimization. The path compaction tool is used in design optimization to reduce the optimizer execution time. Compaction helps readability, usability and reduces synthesis and static timing analyzer (STA) runtime. The aim of path compaction is to reduce the number of constraints the optimizer has to go through during the optimization process. Path compaction has three dimensions. The first is to reduce number of “-through” elements in the constraint, thereby reducing the complexity of constraints developed The second is to combine the paths to reduce the number of constraints. The third is to combine the constraints to reduce the number of constraints to be checked and optimized. Path compaction is used when generating timing exception using timing exception tools.Type: GrantFiled: September 8, 2008Date of Patent: October 18, 2011Assignee: Atrenta, Inc.Inventors: Solaiman Rahim, Manish Bhatia, Housseine Rejouan
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Patent number: 7941679Abstract: A method for computing the power savings in an integrated circuit (IC) design is disclosed. The method computes the difference in power savings between techniques used for clock gating. Based on the computation results, the method outputs a script to control the implementation tool so as to provide for the best implementation clock gating technique in terms of power and area savings.Type: GrantFiled: August 10, 2007Date of Patent: May 10, 2011Assignee: Atrenta, Inc.Inventor: David L. Allen
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Publication number: 20110099400Abstract: Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing is keeping the power dissipation during testing under the allowed power capabilities of the tester power supplies, as the power used during scan test is much higher than that used during functional testing. A method for estimating the power dissipation of scan blocks in a circuit during the design stage is disclosed. Using the results generated, the circuit designer divides the design into an optimum number of scan blocks for test. Thus at-speed scan of the individual or groups of scan blocks can be estimated, during design, for optimizing test time while keeping the test power within acceptable limits.Type: ApplicationFiled: October 22, 2010Publication date: April 28, 2011Applicant: ATRENTA, INC.Inventor: David Allen
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Patent number: 7882483Abstract: The equivalence of two or more constraint files of an integrated circuit (IC) design are checked. The comparison is performed between files at the same stage of design, files that correspond to different stages of the design flow, or between top-level and block-level constraint files.Type: GrantFiled: May 31, 2007Date of Patent: February 1, 2011Assignee: Atrenta, Inc.Inventors: Sridhar Gangadharan, Manish Goel, Pratyush K. Prasoon, Suraj Bharech
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Patent number: 7712061Abstract: A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.Type: GrantFiled: December 18, 2007Date of Patent: May 4, 2010Assignee: ATRENTA, Inc.Inventors: Bhanu Kapoor, Debabrata Bagchi, Sanjay Churiwala