Abstract: A mass storage device includes a storage media with magnetic random access memory (MRAM) devices and a NAND flash interface and NAND flash memory devices that are coupled to the MRAM devices. The storage media has partitions (Logical Units (LUNs)) made of a combination of MRAM and NAND flash memory and further includes a controller with a host interface and a NAND flash interface coupled to the MRAM and NAND flash memory devices through a flash interface. A host is coupled to the controller through the host interface and the storage media communicates attributes to the host, an attribute being associated with one of the partitions, where the host uses the partition based on their attributes to optimize its performance.

Abstract: A memory array is organized into rows and columns of resistive elements and is disclosed to include a resistive element to be read or to be written thereto. Further, a first access transistor is coupled to the resistive element and to a first source line and a second access transistor is coupled to the resistive element and to a second source line, the resistive element being coupled at one end to the first and second access transistors and at an opposite end to a bit line. The memory array further has other resistive elements that are each coupled to the bit line. The resistive element is written to while one or more of the other resistive elements are being read.

Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.

Abstract: A computer system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: A computer system includes a central processing unit (CPU), a system memory coupled to the CPU and including flash tables, and a physically-addressable solid state disk (SSD) coupled to the CPU. The physically-addressable SSD includes a flash subsystem and a non-volatile memory and is addressable using physical addresses. The flash subsystem includes one or more copies of the flash tables and the non-volatile memory includes updates to the copy of the flash tables. The flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressable SSD, wherein the updates to the copy of the flash tables and the one or more copies of the flash tables are used to reconstruct the flash tables upon power interruption.

Abstract: A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.

Abstract: The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element and a method of manufacturing the same is disclosed having a free sub-layer structure with enhanced internal stiffness. A first free sub-layer is deposited, the first free sub-layer being made partially of boron (B), annealing is performed of the STTMRAM element at a first temperature after depositing the first free sub-layer to reduce the B content at an interface between the first free sub-layer and the barrier layer, the annealing causing a second free sub-layer to be formed on top of the first free sub-layer and being made partially of B, the amount of B of the second free sub-layer being greater than the amount of B in the first free sub-layer.

Abstract: A MTJ is sensed by applying a first reference current, first programming the MTJ to a first value using the first reference current, detecting the resistance of the first programmed MTJ, and if the detected resistance is above a first reference resistance, declaring the MTJ to be at a first state. Otherwise, upon determining if the detected resistance is below a second reference resistance, declaring the MTJ to be at a second state. In some cases, applying a second reference current through the MTJ and second programming the MTJ to a second value using the second reference current. Detecting the resistance of the second programmed MTJ and in some cases, declaring the MTJ to be at the second state, and in other cases, declaring the MTJ to be at the first state and programming the MTJ to the second state.

Abstract: A magnetic memory cell is formed including a magneto tunnel junction (MTJ) and an access transistor, which is used to access the MTJ in operation. The access transistor, which is formed on a silicon substrate, includes a gate, drain and source with the gate position substantially perpendicular to the plane of the silicon substrate thereby burying the gate and allowing more surface area on the silicon substrate for formation of additional memory cells.

Abstract: High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.

Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A tuning layer is formed on top of the free layer and a fixed layer is formed on top of the tuning layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

Abstract: A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL, the second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL.

Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.