Abstract: A system and method for displaying frames with dynamically changing display parameters is described herein. The display engine stores new display parameters detected by the decoder in one buffer of a ping pong buffer, while continuing to use another set of display parameters stored in the other ping pong buffer. The display engine switches the buffers when the first frame for which the new display parameters are applicable is to be presented.

Abstract: Signal processing under attenuated transmission conditions. Within an orthogonal signal space, the number of orthogonal signals that are used to transmit information from a transmitter to a receiver is reduced and the transmitted power of each of the now remaining orthogonal signals is modified; this may involve increasing the power of all of the remaining orthogonal signals equally or alternatively modifying them individually. The same modulation used before the reduction may also be used afterwards; within communication systems having multiple transmitter-receiver paths, this will ensure that the communication system's throughput and efficiency will remain unchanged even when one (or more) transmitter-receiver paths are highly attenuated. In addition, robust mode operation is provided for ranging and registering of transmitter devices when entering the communication system.

Abstract: A method of attempting to determine a pitch period of an audio signal using a correlation-based signal derived from the audio signal. The correlation-based signal has known peaks, having been quadratically interpolated and filtered with coefficients that are a function of the interpolation ratio, each corresponding to a respective one of known time lags. The method comprises: identifying a time lag among the time lags; determining if there exists another time lag (i) within a time lag range of a respective one of one or more integer multiples of the identified time lag, and (ii) corresponding to a peak exceeding a peak threshold; and if the determination of step (a) passes, then returning the identified time lag as a time lag indicative of the pitch period.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip processes graphics images organized as windows. The chip obtains data that describes the windows, sorts the data according to the depth of the window on the display, transfers graphics images from memory, and blends the graphics images using alpha values associated with the graphics images.

Abstract: A block encoder flexibly encodes K codes to produce an encoded data block. The block encoder receives an unformatted block of 10 Gigabit Media Independent Interface (XGMII) data. The unformatted block of data includes data and/or K characters, both of which can be located in any position of the unformatted block. The block encoder inserts data characters into a first set of slots of the encoded data block. The block encoder encodes K characters to produce corresponding encoded K characters. Each encoded K character includes a link field, a position field and a recoded value field. The encoded K characters are inserted into a second set of slots of the encoded data block. A synchronization header is attached to the encoded data block to distinguish control blocks from pure data blocks. The header and encoded data block are subsequently scrambled in preparation for transmission.

Abstract: Embodiments of the present invention provide an oscillator circuit having a steady output frequency that is independent of the supplied voltage. This oscillator includes a Schmitt trigger circuit which may be implemented within an integrated circuit of a wireless terminal or other like portable electronic device. The Schmitt trigger circuit receives a threshold voltage input and a second voltage input. The Schmitt trigger circuit generates an output voltage equal to either a first output voltage or a second output voltage based on the results of comparing the threshold voltage input to the second voltage input. An RC network may be coupled to the output of the Schmitt trigger circuit and is operable to supply the second voltage input to the Schmitt trigger circuit.

Abstract: A method of handling data in a memory of a network device is disclosed. The method includes the steps of storing portions of a datagram, being handled by a network device, in a memory, where the memory comprises two logic memory blocks, storing at least two pointers with the portions of the datagram in the memory, where one of the at least two pointers points to a next portion of the memory to be accessed, retrieving the portions of the datagram and the at least two pointers when the network device is ready to act on the datagram, polling a register to determine which of the at least two pointers actually points to the next portion, retrieving the next portion, when necessary and acting on the datagram based on the processing of the datagram by the network device.

Abstract: A disk controller includes a write signal generator for generating a write gate signal based on a media event trigger. A read signal generator generates a read gate signal based on the media event trigger and a read/write bit clock. A read/write channel, adjusts the read gate signal based on the read/write bit clock to avoid a write splice period.

Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

Abstract: Multi-concentric pad (MCP) arrangements provide for increased pad densities on integrated circuits. The multi-concentric pad (MCP) configuration includes a first set of input output (IO) pads and a second set of IO pads, both disposed on an integrated circuit die. Each IO pad in said first set and said second set of IO pads includes a bond pad for receiving a bond wire connection, and an IO circuit coupled to the bond pad. The IO circuits provide an interface between a signal received at the corresponding bond pad and a core circuit disposed on said IC die. The first set of IO pads are arranged closer to the perimeter of the IC die than the second set of IO pads. Furthermore, the second set of IO pads are arranged so that each IO circuit in the second set of IO pads is closer to the center of the IC die than a corresponding IO circuit in the first set of IO pads.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A network device for processing data on a data network including a plurality of ports, configured to receive data from a data network and to send processed data to the data network via an egress port, a controller interface, configured to communicate with an external controller, a memory management unit, configured store data on and retrieve data from the memory and a metering unit, configured to police a flow of the processed data to be sent to the egress port. The metering unit further includes programmable registers, in communication with the controller interface, configured to be programmed through controller signals sent through the controller interface from the external controller, such at all aspects of the flow of the processed data may be controlled by the external controller.

Abstract: A system and method that computes correlation between a first signal and a second signal. The correlation is computed as a ratio of a numerator and a denominator. The numerator may be computed similar to computing the numerator of the Pearson correlation. The denominator may be computed by multiplying the variance of the second signal and the difference between the maximum and minimum value of the first signal. A threshold, which may be programmable, may be used to determine if the first and second signal match by comparing the numerator and the product of the threshold and the denominator. If the numerator is larger than the product then the first signal and the second signal match, otherwise, there is no match. The first signal may be a sliding window of a signal. The window may be slid over the signal until a match is found between the window and the second signal.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: The present invention provides a multi-branch equalizer processing module operable to cancel interference associated with received radio frequency (RF) burst(s). This multi-branch equalizer processing module includes both a first equalizer processing branch and a second equalizer processing branch. The first equalizer processing branch is operable to be trained based upon known training sequences and equalize the received RF burst. This results in soft samples or decisions which in turn may be converted to data bits. The soft samples are processed with a de-interleaver and channel decoder, where the combination is operable to produce a decoded frame of data bits from the soft samples. A re-encoder may re-encode the decoded frame to produce re-encoded or at least partially re-encoded data bits. An interleaver then processes the at least partially re-encoded data bits to produce and at least partially re-encoded burst.

Abstract: A system and method that determine a portion of video data with relevant information about that video to be used in statistical calculations associated with the video. The method may comprise determining the starting line and ending line of the portion of video data with the relevant information. The remaining portion of the video data may comprise information that may contain no statistical information. The remaining portion may be a vertical blanking interval.

Abstract: A system and method for synchronizing sub-carriers in a signal processing system. Various aspects of the present invention may comprise method steps and structure that receive a sampled signal. Various aspects may produce a synchronization signal based on the sampled signal. Various aspects may generate and store a cropped version of the received sampled signal. Various aspects may read a cropped sampled signal from memory that corresponds to the received sampled signal. Various aspects may generate a restored sampled signal by adding samples to the cropped sampled signal read from memory. Various aspects may, based on the synchronization signal, output the restored sampled signal coarsely synchronized to the received sampled signal. Various aspects may determine a phase difference between the output restored sampled signal and the output received sub-carrier. Various aspects may adjust the phase of the restored sampled signal in response to the determined phase difference.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A new topology for a buck-boost switching regulator is provided herein. Embodiments provide an efficient buck-boost switching regulator that provides a regulated output voltage from an unregulated input voltage. Embodiments include a buck-boost switching regulator topology, where the operating mode is determined separately from the pulse-width modulated (PWM) control signal. This topology, in one embodiment, provides a better transient response than typical buck-boost switching regulator topologies, where PWM control circuitry and operating mode circuitry are combined. Furthermore, embodiments provide a buck-boost switching regulator that allows for high efficiency when the output voltage is close to the input voltage.