Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit is described. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A network device for processing data on a data network includes a plurality of ports, configured to receive data from a data network and to send processed data to the data network, a memory management unit configured store data on and retrieve data from the memory and a multi-part parser configured to parse the data received. The multi-part parser comprises several parsing blocks configured to serially parse the data, with each block designated to parse particular values and where each block but a first block receives parsed data from a prior block with the particular values at a zero offset position.

Abstract: Aspects of the invention provide a method and system for reducing signal distortion within an on-chip transitive module. In response to receipt of a signal bearing at least one external clock frequency, at least one harmonic signal of the signal bearing the at least one external clock frequency may be generated. At least one synchronization clock frequency signal may be created from the generated at least one harmonic signal. The synchronization clock frequency signal may subsequently be supplied to at least one power source. Accordingly, the at least one power source may serve as an input power source to at least one on-chip system component of the transitive module with. In this regard, an output of the at least one power source may have at least a frequency attribute of the synchronization clock frequency signal. The synchronization clock frequency signal may reduce signal distortion produced by the at least one power source.

Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to the saturation signal.

Abstract: An integrated circuit (IC) includes at least one baseband section, at least one radio frequency (RF) section, and an interface module. The interface module is operable to couple the at least one baseband section to the at least one RF section, wherein the interface module includes an analog interface module and a digital interface module.

Abstract: An IC includes an RF front end, a down conversion module, an up conversion module, and a local oscillation generating module. The RF front end includes a receive section, a transmit section, and an interference reduction module. The receive section receives an inbound RF signal within a receive frequency band and the transmit section transmits an outbound RF signal within a transmit frequency band. The interference reduction module is coupled to at least one of the receive section and the transmit section and facilitates at least one of: attenuating energy of the outbound RF signal within the receive frequency band based on a transmit local oscillation or a receive local oscillation; and attenuating energy of the inbound RF signal within the transmit frequency band based on the transmit local oscillation or the receive local oscillation.

Abstract: An integrated circuit includes a first RF section, a second RF section, a baseband section, and an antenna coupling matrix. The antenna coupling matrix is coupled to: in a first mode, couple the first RF section to a first antenna structure and couple the second RF section to a second antenna structure; in a second mode, couple the first RF section to the first antenna structure and to the second antenna structure; and in a third mode, couple the second RF section to the first antenna structure and to the second antenna structure.

Abstract: A variable gain amplifier including a stage. The stage having a set of switchable differential pairs. The stage providing a gain range to a signal and adjusting a gain of the signal. At least one differential pair in each stage is permanently enabled. The variable gain amplifier may include a plurality of cascaded stages including the stage. In addition, the variable gain amplifier may be adjusted through an interleaved thermometer coding method.

Abstract: An integrated circuit (IC) includes an RF section, a DSP, and a plurality of processors. The RF section and the DSP process an inbound RF signal to produce inbound data and process outbound data to produce an outbound RF signal. In addition, the DSP converts an outbound analog audio signal into an outbound digital audio signal and converts an inbound digital audio signal into an inbound analog audio signal. A first processor converts the inbound data into the inbound digital audio signal and converts the outbound digital audio signal into the outbound data. A second processor performs a user application that includes at least one of generation of the inbound analog audio signal and generation of the outbound analog audio signal and performs an operating system algorithm to coordinate operation of the user application.

Abstract: In a communication system, Huffman coding techniques are used to obtain shaping gains for an improvement in data transmission rates. More particularly, a novel method of Huffman shaping is described that achieves a shaping gain of greater than 1 dB. The shaping gain results in a higher data rate transmission in a communication system where transmitted power is constrained.

Abstract: Apparatus and method are disclosed for constructing an eye pattern from a serial data signal within a receiver used in a serial data communication system. The receiver is used to receive the serial data signal and generates an internal clock signal from the serial data signal using, at least in part, a CDR circuit. Timing data corresponding to a current phase of the clock signal is also generated within the receiver using an interpolator circuit. The serial data signal is sampled by an ADC using the clock signal to generate sampled data. The sampled data and timing data are processed within the receiver by a data processor to generate the eye pattern. The resultant eye pattern may be analyzed within the receiver with respect to at least one characteristic of the eye pattern. At least one parameter of the receiver may be adjusted in response to the foregoing analysis.

Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed.

Abstract: A method to reduce transmitted output power and the battery consumption is provided. This involves first determining the required output level. The amplitude of the input signal provided to a PA driver may be based on the required output power level. This amplitude may be set by a PGA. A number of cascode bias signals are also provided to the PA driver. These cascode bias signals are based on the required output power level as well. Reducing the cascode bias signals by enabling/disabling circuits within the PA driver allows power consumption of the wireless device to be reduced.

Abstract: A disk formatter includes an address module for creating disk block address data corresponding to a disk sector of a disk drive. A sector write module initiates a physical mode write operation to the disk sector that incorporates the corresponding disk block address data.

Abstract: An apparatus and method for transmitting a signal from a plurality of antennas. The apparatus includes an outer encoder configured to encode a stream of data according to a turbo multiple trellis coded modulation scheme, and generate a plurality of channel-coded symbol streams. The apparatus also includes an inner encoder serially concatenated with the outer encoder. The inner encoder is configured to receive the channel-coded symbol streams and provide space-time coding to the channel-coded symbol streams, thereby generating a plurality of space-time-channel-coded symbol streams. A plurality of antennas coupled are to the inner encoder, and each of the plurality of antennas is configured to transmit one of the plurality of space-time-channel-coded symbol streams.

Abstract: A packet-based, hierarchical communication system, arranged in a spanning tree configuration, is described in which wired and wireless communication networks exhibiting substantially different characteristics are employed in an overall scheme to link portable or mobile computing devices. The network accommodates real time voice transmission both through dedicated, scheduled bandwidth and through a packet-based routing within the confines and constraints of a data network. Conversion and call processing circuitry is also disclosed which enables access devices and personal computers to adapt voice information between analog voice stream and digital voice packet formats as proves necessary. Routing pathways include wireless spanning tree networks, wide area networks, telephone switching networks, internet, etc., in a manner virtually transparent to the user.

Abstract: A system, method and computer program product is provided that allows an end user to monitor and/or control various data streams appearing on one or more customer premises equipment (CPE) interfaces of a residential gateway, even where the data streams are of different types such as voice, video or computer data. The invention provides a user interface, implemented as part of a CPE device or as a stand-alone device, that is accessed by an end user to transmit commands to a residential gateway. A processor within the residential gateway executes gateway monitoring and control software that receives the commands and, in response, performs the necessary routing and conversion of data streams to execute the desired monitoring and/or control functions.

Abstract: Methods and systems for detecting defects in serial link transceivers. Defect detection includes detecting open circuits in one or more of the transmission lines, detecting short circuits between one or more of the transmission lines and a power supply, detecting short circuits between the transmission lines, or detecting short circuits across optional AC-couplings in the transmission lines. The detection can include direct or indirect detection of voltage or current.

Abstract: A differential amplifier is configured in a cascode configuration that includes input transistors that are connected to corresponding cascode transistors. The gates of the cascode transistors are tied together to form a common bias for the cascode devices. The input transistors of the differential amplifier receive a differential input signal that is amplified and outputted to an output circuit that is connected to the cascode transistors. The cascode devices require a bias voltage for proper operation. Preferably, the bias voltage puts the cascode devices into the saturation region. The gates of cascode devices are coupled together and connected to a bias terminal. In embodiments of the invention, the bias terminal is connected to another terminal of the chip to provide the bias for the cascode devices. This can include the input and output nodes if they have a well-defined and relatively fixed voltage.