Abstract: Methods and systems for detecting defects in serial link transceivers. Defect detection includes detecting open circuits in one or more of the transmission lines, detecting short circuits between one or more of the transmission lines and a power supply, detecting short circuits between the transmission lines, or detecting short circuits across optional AC-couplings in the transmission lines. The detection can include direct or indirect detection of voltage or current.

Abstract: Computing optimal Linear Equalizer (LE) coefficients gopt from a channel estimate h. A channel impulse response h is first estimated based upon either a known training sequence or an unknown sequence. The channel estimate is formulated as a convolution matrix H. The convolution matrix H is then related to the LE coefficients in a matrix format equation, the matrix format equation based upon the structure of the LE, the convolution matrix, and an expected output of the LE. A Fast Transversal Filter (FTF) algorithm is then used to formulate a recursive least squares solution to the matrix format equation. Computing the recursive least squares solution yields the LE coefficients using structured equations.

Abstract: A network switch that includes an address resolution table and a VLAN table. The address resolution table comprises a VLAN identifier (ARL VID) in less significant bits, a MAC address, and an action code, wherein each VLAN identifier in the address resolution table is unique. The VLAN table is used for storing information related to frame forwarding. The VLAN table includes a VLAN identifier (VLAN VID) in more significant bits, a forward map and an un-tag map. The ARL VID is used to access an associated entry in the VLAN table.

Abstract: A system and method is provided for generating and using multiple synchronized local program timestamps in a media processing system. The system includes an input processor, one or more local timestamp insertion modules, one or more parsers, and an input buffer. Each local program timestamp module includes a clock reference recovery module, a local program clock synchronized to the system time clock of a program source, and a timestamp generator. The system also includes one or more processing modules such as record modules, transmission modules, and display modules. When a data packet is received by the media processing system, the local timestamp insertion module appends a timestamp to the data packet. The timestamp is based on the synchronized local program clock for the program associated with the data packet. The processing modules utilize the synchronized local timestamps and their associated local program clock in a variety of applications.

Abstract: A multi-port transceiver includes a transmitter and receiver for each port. The invention is a test method and apparatus for testing individual components in the transmit and receive paths. Specifically, the invention includes a method of testing the full range of a programmable gain amplifier (PGA) and an analog to digital converter (ADC) in the receive path of each port. This is accomplished by connecting the transmitter of one port directly to the receiver of a second port, and varying the amplitude of the transmitter over a range of gain settings of the PGA while examining if the dynamic range of the receiver has been exceeded.

Abstract: An apparatus and method is disclosed to substantially reduce phase noise introduced in fractional-N phase-locked loop (PLL) through feedback modulation. A fractional frequency divider is introduced in the feedback path of the PLL to generate a true fractional division factor with finite fractional steps to increase the resolution of the PLL by a factor equal to the inverse of the finite step size in the fractional frequency divider. Increasing the resolution of the PLL reduces phase noise. The fractional frequency divider uses the true fractional division factor to divide the frequency of a single output of a multi-phased voltage controlled oscillator (VCO) by the fractional division factor to match the frequency of the divided feedback signal to frequency a reference signal.

Abstract: A radio transceiver device includes circuitry for radiating electromagnetic signals at a very high radio frequency both through space, as well as through wave guides that are formed within a substrate material. In one embodiment, the substrate comprises a dielectric substrate formed within a board, for example, a printed circuit board. In another embodiment of the invention, the wave guide is formed within a die of an integrated circuit radio transceiver. A plurality of transceivers with different functionality is defined. Substrate transceivers are operable to transmit through the wave guides, while local transceivers are operable to produce very short range wireless transmissions through space. A third and final transceiver is a typical wireless transceiver for communication with remote (non-local to the device) transceivers. Additionally, a multi-mode transceiver is operable to configure transmit and receive circuitry based upon transmission path.

Abstract: A wireless device includes at least one antenna, a plurality of shared signal path components coupled to the at least one antenna, the plurality of shared signal path components including a shared adjustable gain element, e.g., Low Noise Amplifier (LNA), Power Amplifier (PA), etc., a first wireless interface, e.g. Wireless Local Area Network interface coupled to the plurality of shared signal path components, and a second wireless interface, e.g., Wireless Personal Area Network interface, coupled to the plurality of shared signal path components. During a first operational period, the first wireless interface controls gain of the shared adjustable gain element and during a second operational period that differs from the first operational period, the second wireless network interface controls gain of the shared adjustable gain element. With another embodiment the first wireless interface and/or the second wireless interface each includes shared adjustable gain elements for transmit and receive diversity.

Abstract: A system and method for mirroring power over Ethernet (PoE) registers in physical layer devices (PHYs) over a single isolation boundary. PHYs in a PoE system can be arranged in a master/slave configuration. In this configuration, a master PHY can be designed to communicate with the power source equipment controllers via a single isolation device.

Abstract: An integrated circuit includes a on-chip pressure sensing circuit that generates a pressure signal based on a pressure of the integrated circuit. An RF transceiver generates an outbound RF signal from outbound data and to generate inbound data from an inbound RF signal, based on the pressure signal.

Abstract: Cancellation of interference in a communication system with application to S-CDMA. A relatively straight-forward implemented and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination selectively with each of the input spread signals in a multiple access communication system. If desired, the predetermined number of unused codes is always the same in each implementation. Alternatively, the predetermined number of unused codes is selected from within a reordered code matrix using knowledge that is shared between the two ends of a communication system, such as between the CMs and a CMTS. While the context of an S-CDMA communication system having CMs and a CMTS is used, the solution is generally applicable to any communication system that seeks to cancel narrowband interference. Several embodiments are also described that show the generic applicability of the solution across a wide variety of systems.

Abstract: A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format, the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: A system for processing wireless data packets allows for processing packets allows consolidation of security processing. Security processing is performed in accordance with multiple security policies. This processing is done in a single front end processing block. Different security processes can be performed in parallel. Processing overhead is reduced by eliminating the need to redundantly check packet characteristics to assess the different security requirements imposed by security policies. Further, the present invention also substantially reduces the CPU cycles required to transport data back and forth from memory to a cryptographic coprocessor.

Abstract: A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a “legitimate” Ethernet-type frame. The status field can be a “push”-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.

Abstract: A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes multiple comparators to provide constant bandwidth tracking and step response, as well as fine granularity for decision directed convergence. In one embodiment, an odd number of comparators is used with square-law scaling at the output to achieve constant bandwidth step response for a wide range of input amplitude changes.

Abstract: A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Abstract: A system for implementing personal video recording, in which integrated drive electronics are incorporated in set-top box logic, instead of with a hard disk drive. This allows the set-top box logic to communicate directly to the hard disk, so that no intervening bus is necessary.

Abstract: In an embodiment, an analog to digital converter (ADC) has a dynamic power circuit. The ADC has a track-and-hold circuit with an output and a track mode. The ADC also has a comparator with an input. A preamplifier is coupled between the track-and-hold output and the comparator input. At least one of a preamplifier current and a comparator current are limited during the track mode to reduce ADC power consumption.