Abstract: An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip filter component that forms a programmable filter with the at least one off-chip filter component. The programmable filter is programmable based on a control signal. An RF receiver generates inbound data in response to a received signal from the programmable filter.

Abstract: A (radio frequency) RF reception system includes an off-chip antenna interface and an integrated circuit. The an off-chip antenna interface includes at least one first off-chip impedance matching component, a filter, and at least one second off-chip impedance matching component. The integrated circuit includes an on-chip antenna interface that forms a first programmable impedance matching network with the at least one first off-chip impedance matching component, and forms a second programmable impedance matching network with the at least one second off-chip impedance matching component. The first programmable impedance matching network and the second programmable impedance matching network are programmable based on a frequency selection signal.

Abstract: A radio frequency (RF) transceiver device includes a processing module, memory, a baseband processing module, an RF section, an RF bus, and an RF bus controller. The processing module and the memory include an RF bus transceiver. The baseband processing module is coupled to convert outbound data into an outbound symbol stream and to convert an inbound symbol stream into inbound data. The RF section is coupled to convert the outbound symbol stream into an outbound RF signal and to convert an inbound RF signal into the inbound symbol stream. The RF bus controller is coupled to control access to an RF bus for providing the outbound data as an RF bus outbound data signal from the processing module RF bus transceiver or from the memory RF bus transceiver and to control access to the RF bus for providing the inbound data as an RF bus inbound data signal to the processing module RF bus transceiver or to the memory RF bus transceiver.

Abstract: An on-chip inductor includes a first turn on a first dielectric layer and a via, coupled to the first turn. A second turn on a second dielectric layer, is coupled to the first dielectric layer and via. The first dielectric layer includes at least one removed dielectric section where a portion of the first dielectric is removed between the first turn and the second turn, improving the magnetic coupling between the first turn and the second turn.

Abstract: Methods for assembling a die-down array integrated circuit (IC) device packages with enhanced thermal, electrical, and input/output properties are presented. The method includes coupling a first surface of a substrate to a first surface of a heat spreader, mounting a first surface of an IC die to the first surface of the heat spreader within a central cavity of the substrate, coupling a plurality of bond pads on a second surface of the IC die to corresponding bond pads on a second surface of the substrate with a plurality of wire bonds, and coupling a first surface of an interposer to the second surface of said IC die. A central opening is open at the first surface of the substrate and the second surface of the substrate. The central opening overlaps the central cavity formed in the first surface of the heat spreader. A plurality of electrically conductive bumps on the second surface of the IC die are coupled to corresponding bond pads on the first surface of said interposer.

Abstract: A reception system includes an antenna that receives and inbound RF signal. An antenna interface includes a low noise amplifier that generates an amplified received signal, based on the inbound RF signal. A transmission path coupled carries the amplified received signal to an integrated circuit, that includes a RF receiver with an RF front end that generates a desired RF signal from the amplified received signal, a down conversion module, that generates a down converted signal from the desired RF signal and a receiver processing module that generates inbound data for at least one communication application.

Abstract: A method for accessing an RF begins by determining whether information is to be transmitted via the RF bus. The method continues by determining whether the RF bus is available when the information is to be transmitted via the RF bus. The method continues by securing access to the RF bus when the RF bus is available. The method continues by converting the information into RF bus signal and by transmitting the RF bus signal via the RF bus when access to the RF bus is secured.

Abstract: An RF transceiver system includes an RF transmitter that generates a transmit signal and an RF receiver that receives a received signal. A diplexer couples the transmit signal to an antenna, produces the received signal based on an inbound RF signal to the antenna, and isolates the transmit signal from the received signal. A mismatch detection module detects an impedance mismatch at the output of the RF transmitter by processing the transmit signal and the received signal and generates a mismatch feedback signal in response to an amount of detected mismatch. A processing module controls the amount of mismatch at the output of the RF transmitter in response to the mismatch feedback signal.

Abstract: An integrated circuit includes an on-chip antenna interface, coupled to an off-chip antenna interface having at least one off-chip impedance matching component, that forms a programmable impedance matching network with the at least one off-chip impedance matching component. The programmable impedance matching network is programmable based on a control signal. An RF receiver, coupled to the programmable impedance matching network, that generates inbound data in response to a received signal from the programmable impedance matching network.

Abstract: A device includes a first integrated circuit, a second integrated circuit and an RF bus controller. Each of the first and second ICs includes a radio frequency (RF) bus transceiver. The RF bus controller is coupled to control intra-device RF communications between the RF bus transceivers of the first and second ICs.

Abstract: A voice data and RF integrated circuit (IC) includes a memory module that stores a least one application as a plurality of operational instructions, the at least one application having a plurality of power modes that each correspond to one of a plurality of use characteristics. A processing module executes the plurality of operational instructions, determines a selected one of the plurality of power modes based on current use characteristics of the at least one application, and generates a power mode signal based on the selected one of the plurality of power modes. An on-chip power management circuit receives the power mode signal and generates a plurality of power supply signals based on the power mode signal.

Abstract: A digital IF demodulator includes an analog-to-digital (A/D) converter that receives an analog IF signal and converts it to a digital IF signal. A parallel multiplier then down-converts the digital IF signal to a baseband signal having a video component and an audio component. The frequency down-conversion uses a parallel multiplier driven by an outer feedback loop that corrects gross frequency errors in said digital IF signal. The digital IF demodulator also includes a video recovery circuit that selects the video component from the baseband signal and further down-converts the baseband signal to a video baseband using a video complex mixer driven by an inner feedback loop that corrects fast phase perturbations in the video recovery circuit. Finally, the digital IF demodulator includes an audio recovery circuit that (i) receives said baseband signal from the parallel multiplier, and (ii) down-converts the audio component to an audio baseband signal using an audio complex mixer.

Abstract: A loop filter for use in a frequency synthesizer provides improved spurious performance using switched capacitors. The loop filter includes a first switched capacitor having a first capacitance value and which is operable to charge to a first voltage corresponding to a current pulse indicative of a difference in phase or frequency between a reference signal and a feedback signal. The loop filter further includes a second switched capacitor having a second capacitance value and which is operable to charge to a second voltage from the first voltage and produce a control voltage based upon the second voltage. The loop filter has a bandwidth determined by a ratio of the second capacitance value to the first capacitance value.

Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. The decoding can be performed on signals whose various symbols have been mapped to multiple modulations (constellations and mappings) according to a rate control sequence. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding to generate the signal that is subsequently decoded. Either one or both of an encoder that generates the signal and a decoder that decodes the signal may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

Abstract: There is disclosed a receiver for receiving a multi-band DMT signal. The receiver includes a plurality of demodulators, each demodulator having a discrete Fourier transform and being provided to demodulate a respective one of a plurality of bands in the multi-band signal, the multi-band signal being modulated in an inverse discrete Fourier transform. A method of demodulating a multi-band signal is also provided.

Abstract: In a method and system for 3D comb synchronization and alignment of standard and non-standard video signals, a coarse synchronization is performed on a bottom frame, a current frame, and a top frame based on a bottom frame field count. The current frame is assigned the frame transferred immediately prior to a bottom frame whereas the top frame is assigned the frame transferred two frames. A current frame window signal and a top frame window signal may be used to lock the current frame and the top frame to a bottom frame vertical sync signal. After coarse synchronization, the video frames are finely aligned by correlating a phase difference between the subcarrier signals in each frame and modifying the phase difference until the correlation results in a specified phase locked value range. This method and system may facilitate the handling of video stream switching and non-standard data streams.

Abstract: A method of sharing information among a plurality of stations on a communications network, each of the stations being capable of transmitting and receiving frames over the communications network. A group of agreed-upon flags is established, periodic timing is provided in each station that expires after an interval, and a common frame format is defined providing the capability of specifying a current transmit flag set, an old transmit flag set, and a current receive flag set. Each station maintains: a current transmit state set a recent and previous timer expiration set and a current and previous transmit received set. A control frame is generated and transmitted by a transmitting station to all other stations on the communications network each time a flag in a logical union of current transmit flag sets is set and upon the expiration of the timer in the transmitting station.

Abstract: A system and method of concealing bit errors in a signal are provided. An exemplary method detects bit errors in an input signal having at least a current signal segment and a previous signal segment. The previous signal segment has a log-gain value qlg(m?1) and immediately precedes the current signal segment. The method comprises estimating a level lvl(m?1) of the input signal and determining a log-gain value qlg(m) of the current signal segment within the input signal. The method also comprises determining a difference between the gain value of the current signal segment and the previous signal segment and determining whether the difference exceeds a threshold. wherein the threshold is adaptive to the input signal level.

Abstract: One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.

Abstract: A method determines RW head radial position relative to tracks within a magnetic data disc. This involves sensing both a S-burst signal and a P-burst signal with the RW head. The S-burst signal and P-burst signal are associated with a two-burst servo pattern on the magnetic disc. The S-burst pattern has a phase that remains constant radially across tracks within the magnetic disc. The P-burst has a second phase that rotates radially across tracks within the magnetic disc. By determining a phase difference between a sensed S-burst signal and P-burst signal, it is possible to determine the RW head radial position relative to the tracks on the magnetic disc.